headshot of Yiran Chen

Yiran Chen

Adjunct Associate Professor
Electrical and Computer Engineering

about

(2013) NSF CAREER Award.

(2013) Best Paper Nomination, Asia and South Pacific Design Automation Conference (ASP-DAC) for the paper titled "Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache".

(2012) 49th Design Automation Conference A. Richard Newton Scholarship for Ph.D. student Wujie Wen.

(2011) Best Paper Nomination, Asia and South Pacific Design Automation Conference (ASP-DAC) for the paper titled "Geometry Variations Analysis of TiO2 Thin Film and Spintronic Memristors".

(2011 - 2012) 3. Two Times Air Force Visiting Faculty Research Program (VFRP) Fellowship, AFRL/RIB, Rome, NY, 2011, 2012. (Selected extensions of $10,000 and $8000 grants are also approved for Sep.-Dec. 2011, and 2012, respectively).

(2010) 6. Best Paper Award, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) for the paper titled "Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM".

(2010) 7. Best Paper Nomination, Design, Automation & Test in Europe Conference and Exhibition (DATE) for the paper titled "A Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM)".

(2010) Best Paper Nomination, the 11th International Symposium on Quality Electronic Design (ISQED) for the paper titled "Scalability of PCMO-based Resistive Switch Device in DSM Technologies".

(2008) Best Paper Award, the 9th International Symposium on Quality Electronic Design (ISQED) for paper titled "Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)".

(2007) Finalists of Prestigious 2007 DesignVision Awards for PrimeTimeVX, International Engineering Cons.

(2006) PrimeTimeVX - EDN 100 Hot Products Distinction, Synopsys Inc..

(2006) The hot 100 products of 2006 for PrimeTimeVX, EDN (www.edn.com).

(2005) Best Paper Nomination, the 6th International Symposium on Quality Electronic Design (ISQED) for the paper titled "Power Supply Noise-aware Scheduling and Allocation for DSP Synthesis".

Ph.D., Electrical and Computer engineering, Purdue University, 2005

M.S., Electronic Engineering, Tsinghua University, 2001

B.S., Electronic Engineering, Tsinghua University, 1998

Chai, X., Fu, X., Gan, Z., Zhang, Y., Lu, Y., & Chen, Y. (2020). An efficient chaos-based image compression and encryption scheme using block compressive sensing and elementary cellular automata. Neural Computing and Applications, 32(9), 4961-4988.Springer Science and Business Media LLC. doi: 10.1007/s00521-018-3913-3.

Chai, X., Fu, X., Gan, Z., Lu, Y., & Chen, Y. (2019). A color image cryptosystem based on dynamic DNA encryption and chaos. Signal Processing, 155, 44-62.Elsevier BV. doi: 10.1016/j.sigpro.2018.09.029.

Chai, X., Gan, Z., Yuan, K., Chen, Y., & Liu, X. (2019). A novel image encryption scheme based on DNA sequence operations and chaotic systems. Neural Computing and Applications, 31(1), 219-237.Springer Science and Business Media LLC. doi: 10.1007/s00521-017-2993-9.

Chen, Y. (2019). Reshaping Future Computing Systems With Emerging Nonvolatile Memory Technologies. IEEE Micro, 39(1), 54-57.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/mm.2018.2885588.

Li, S., Xiao, N., Wang, P., Sun, G., Wang, X., Chen, Y., Li, H.H., Cong, J., & Zhang, T. (2019). RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses. IEEE Transactions on Computers, 68(2), 239-254.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tc.2018.2868368.

Yang, J., Wang, X., Zhou, Q., Wang, Z., Li, H., Chen, Y., & Zhao, W. (2019). Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38(1), 57-69.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tcad.2018.2802870.

Zhou, Y., Hu, X., Wang, L., Duan, S., & Chen, Y. (2019). Markov Chain Based Efficient Defense Against Adversarial Examples in Computer Vision. IEEE Access, 7, 5695-5706.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/access.2018.2889409.

Bayram, I., & Chen, Y. (2018). NV-TCAM: Alternative designs with NVM devices. Integration, 62, 114-122.Elsevier BV. doi: 10.1016/j.vlsi.2018.02.003.

Chai, X., Zheng, X., Gan, Z., Han, D., & Chen, Y. (2018). An image encryption algorithm based on chaotic system and compressive sensing. Signal Processing, 148, 124-144.Elsevier BV. doi: 10.1016/j.sigpro.2018.02.007.

Chang, N., Faruque, M.A., Shao, Z., Xue, C.J., Chen, Y., & Baek, D. (2018). Survey of Low-Power Electric Vehicles: A Design Automation Perspective. IEEE Design & Test, 35(6), 44-70.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/mdat.2018.2873475.

Chen, L., Li, C., & Chen, Y. (2018). A Forgetting Memristive Spiking Neural Network for Pavlov Experiment. International Journal of Bifurcation and Chaos, 28(06), 1850080.World Scientific Pub Co Pte Lt. doi: 10.1142/s0218127418500803.

Chen, Y., Li, H.H., Wu, C., Song, C., Li, S., Min, C., Cheng, H.P., Wen, W., & Liu, X. (2018). Neuromorphic computing's yesterday, today, and tomorrow - an evolutional view. INTEGRATION-THE VLSI JOURNAL, 61, 49-61.Elsevier BV. doi: 10.1016/j.vlsi.2017.11.001.

Guo, J., Min, C., Cai, T., & Chen, Y. (2018). Improving Write Performance and Extending Endurance of Object-Based NAND Flash Devices. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 17(1), 1-26.Association for Computing Machinery (ACM). doi: 10.1145/3105924.

Hassan, A.M., Khalaf, A.F., Sayed, K.S., Li, H.H., & Chen, Y. (2018). Real-Time Cardiac Arrhythmia Classification Using Memristor Neuromorphic Computing System. Annu Int Conf IEEE Eng Med Biol Soc, 2018, 2567-2570.IEEE. doi: 10.1109/EMBC.2018.8512868.

Liu, Z., Mao, M., Liu, T., Wang, X., Wen, W., Chen, Y., Li, H., Wang, D., Pei, Y., & Ge, N. (2018). TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(10), 1985-1998.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tcad.2017.2783860.

Lu, Y., Berg, A.C., & Chen, Y. (2018). Low‐Power Image Recognition Challenge. AI Magazine, 39(2), 87-88.Wiley. doi: 10.1609/aimag.v39i2.2782.

Wang, D., Ma, L., Zhang, M., An, J., Li, H.H., & Chen, Y. (2018). Shift-Optimized Energy-Efficient Racetrack-Based Main Memory. Journal of Circuits, Systems and Computers, 27(05), 1850081.World Scientific Pub Co Pte Lt. doi: 10.1142/s0218126618500810.

Yan, B., Chen, Y., & Li, H. (2018). Challenges of memristor based neuromorphic computing system. Science China Information Sciences, 61(6).Springer Science and Business Media LLC. doi: 10.1007/s11432-017-9378-3.

Zhang, L., Song, W., Yang, J.J., Li, H., & Chen, Y. (2018). A compact model for selectors based on metal doped electrolyte. APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING, 124(4).Springer Science and Business Media LLC. doi: 10.1007/s00339-018-1706-2.

Chai, X., Chen, Y., & Broyde, L. (2017). A novel chaos-based image encryption algorithm using DNA sequence operations. Optics and Lasers in Engineering, 88, 197-213.Elsevier BV. doi: 10.1016/j.optlaseng.2016.08.009.

Chai, X., Gan, Z., Chen, Y., & Zhang, Y. (2017). A visually secure image encryption scheme based on compressive sensing. Signal Processing, 134, 35-51.Elsevier BV. doi: 10.1016/j.sigpro.2016.11.016.

Chai, X., Gan, Z., Lu, Y., Chen, Y., & Han, D. (2017). A novel image encryption algorithm based on the chaotic system and DNA computing. International Journal of Modern Physics C, 28(05), 1750069.World Scientific Pub Co Pte Ltd. doi: 10.1142/s0129183117500693.

Chai, X., Gan, Z., Yang, K., Chen, Y., & Liu, X. (2017). An image encryption algorithm based on the memristive hyperchaotic system, cellular automata and DNA sequence operations. Signal Processing: Image Communication, 52, 6-19.Elsevier BV. doi: 10.1016/j.image.2016.12.007.

Chai, X.L., Gan, Z.H., Yuan, K., Lu, Y., & Chen, Y.R. (2017). An image encryption scheme based on three-dimensional Brownian motion and chaotic system. CHINESE PHYSICS B, 26(2), 020504.IOP Publishing. doi: 10.1088/1674-1056/26/2/020504.

Chen, X., Khoshavi, N., DeMara, R.F., Wang, J., Huang, D., Wen, W., & Chen, Y. (2017). Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache. IEEE TRANSACTIONS ON COMPUTERS, 66(5), 786-798.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2016.2625245.

Chen, Y., Kuo, T.W., & de Salvo, B. (2017). Guest Editors’ Introduction: Critical and Enabling Techniques for Emerging Memories. IEEE Design & Test, 34(3), 6-7.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/mdat.2017.2682253.

Chen, Y., Li, H.H., Bayram, I., & Eken, E. (2017). Recent Technology Advances of Emerging Memories. IEEE DESIGN & TEST, 34(3), 8-22.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MDAT.2017.2685381.

Chen, Y.C., Wang, Y., Zhang, W., Chen, Y., & (Helen) Li, H. (2017). In-place Logic Obfuscation for Emerging Nonvolatile FPGAs. In Fundamentals of IP and SoC Security. (pp. 277-293).Springer International Publishing. doi: 10.1007/978-3-319-50057-7_11.

Eken, E., Bayram, I., Zhang, Y., Yan, B., Wu, W., Li, H.H., & Chen, Y. (2017). Giant Spin-Hall assisted STT-RAM and logic design. INTEGRATION-THE VLSI JOURNAL, 58, 253-261.Elsevier BV. doi: 10.1016/j.vlsi.2017.04.002.

Guo, J., Wang, D., Shao, Z., & Chen, Y. (2017). Data-Pattern-Aware Error Prevention Technique to Improve System Reliability. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 25(4), 1433-1443.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TVLSI.2016.2642055.

Guo, J., Wen, W., Hu, J., Wang, D., Li, H., & Chen, Y. (2017). FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 36(7), 1167-1180.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2016.2619480.

Hu, M., Chen, Y., Yang, J.J., Wang, Y., & Li, H.H. (2017). A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 36(8), 1353-1366.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2016.2618866.

Li, H., & Chen, Y. (2017). Nonvolatile Memory Design. 1-189.CRC Press. doi: 10.1201/b11354.

Li, H.H., Chen, Y., Liu, C., Strachan, J.P., & Davila, N. (2017). Looking Ahead for Resistive Memory Technology A broad perspective on ReRAM technology for future storage and computing. IEEE CONSUMER ELECTRONICS MAGAZINE, 6(1), 94-103.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MCE.2016.2614523.

Mao, M., Wen, W., Zhang, Y., Chen, Y., & Li, H. (2017). An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory. IEEE Transactions on Computers, 66(9), 1478-1490.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tc.2017.2690855.

Pan, C., Xie, M., Yang, C., Chen, Y., & Hu, J. (2017). Exploiting Multiple Write Modes of Nonvolatile Main Memory in Embedded Systems. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 16(4), 1-26.Association for Computing Machinery (ACM). doi: 10.1145/3063130.

Sun, G., & Chen, Y. (2017). Preface. 10561 LNCS.

Yang, C., Li, H., & Chen, Y. (2017). Security Opportunities in Nano Devices and Emerging Technologies. In Security Opportunities in Nano Devices and Emerging Technologies. (pp. 215-234).CRC Press. doi: 10.1201/9781315265056.

Zhang, P., Li, C., Huang, T., Chen, L., & Chen, Y. (2017). Forgetting memristor based neuromorphic system for pattern training and recognition. NEUROCOMPUTING, 222, 47-53.Elsevier BV. doi: 10.1016/j.neucom.2016.10.012.

Zhang, Y., Wen, W., Li, H., & Chen, Y. (2017). Metallic Spintronic Devices. In Metallic Spintronic Devices. (pp. 71-103).CRC Press. doi: 10.1201/b17238.

Zhang, Y., Yan, B., Wang, X., & Chen, Y. (2017). Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(7), 1181-1192.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tcad.2016.2619484.

Chai, X.L., Gan, Z.H., Lu, Y., Zhang, M.H., & Chen, Y.R. (2016). A novel color image encryption algorithm based on genetic recombination and the four-dimensional memristive hyperchaotic system. CHINESE PHYSICS B, 25(10), 100503.IOP Publishing. doi: 10.1088/1674-1056/25/10/100503.

Chen, L., Li, C., Huang, T., Hu, X., & Chen, Y. (2016). The bipolar and unipolar reversible behavior on the forgetting memristor model. NEUROCOMPUTING, 171, 1637-1643.Elsevier BV. doi: 10.1016/j.neucom.2015.06.067.

Gu, S., Sha, E.H.M., Zhuge, Q., Chen, Y., & Hu, J. (2016). A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(12), 2008-2017.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tcad.2016.2547903.

Liu, X., Mao, M., Liu, B., Li, B., Wang, Y., Jiang, H., Barnell, M., Wu, Q., Yang, J., Li, H., & Chen, Y. (2016). Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 63(5), 617-628.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCSI.2016.2529279.

Sun, G., Zhang, C., Li, P., Wang, T., & Chen, Y. (2016). Statistical Cache Bypassing for Non-Volatile Memory. IEEE TRANSACTIONS ON COMPUTERS, 65(11), 3427-3440.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2016.2529621.

Yang, J., Sun, Z., Wang, X., Chen, Y., & Li, H. (2016). Spintronic Memristor as Interface Between DNA and Solid State Devices. 6, (pp. 212-221).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/JETCAS.2016.2547700.

Yang, J., Wang, P., Zhang, Y., Cheng, Y., Zhao, W., Chen, Y., & Li, H.H. (2016). Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 35(3), 380-393.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2015.2474366.

Chen, Y., Choi, K., & Zhao, W. (2015). Guest Editorial for Special Issue on Emerging Memory Technologies—Modeling, Design, and Applications for Multi-Scale Computing. IEEE Transactions on Multi-Scale Computing Systems, 1(3), 125-126.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tmscs.2015.2505118.

Li, B., Gu, P., Shan, Y., Wang, Y., Chen, Y., & Yang, H. (2015). RRAM-Based Analog Approximate Computing. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 34(12), 1905-1917.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2015.2445741.

Liu, B., Chen, Y., Wysocki, B., & Huang, T. (2015). Reconfigurable Neuromorphic Computing System with Memristor-Based Synapse Design. NEURAL PROCESSING LETTERS, 41(2), 159-167.Springer Science and Business Media LLC. doi: 10.1007/s11063-013-9315-8.

Wang, D.H., Liu, H.P., & Chen, Y.R. (2015). Multi-bit soft error tolerable L1 data cache based on characteristic of data value. Journal of Central South University, 22(5), 1769-1775.Springer Science and Business Media LLC. doi: 10.1007/s11771-015-2695-3.

Wang, P., Eken, E., Zhang, W., Joshi, R., Kanj, R., & Chen, Y. (2015). A Thermal and Process Variation Aware MTJ Switching Model and Its Applications in Soft Error Analysis. In More than Moore Technologies for Next Generation Computer Design. (pp. 101-125).Springer New York. doi: 10.1007/978-1-4939-2163-8_5.

Wen, S., Huang, T., Zeng, Z., Chen, Y., & Li, P. (2015). Circuit design and exponential stabilization of memristive neural networks. NEURAL NETWORKS, 63, 48-56.Elsevier BV. doi: 10.1016/j.neunet.2014.10.011.

Wen, W., Zhang, Y., & Chen, Y. (2015). Statistical Reliability/Energy Characterization in STT-RAM Cell Designs. In Spintronics-based Computing. (pp. 201-230).Springer International Publishing. doi: 10.1007/978-3-319-15180-9_7.

Zhang, L., Ge, N., Yang, J.J., Li, Z., Williams, R.S., & Chen, Y. (2015). Low voltage two-state-variable memristor model of vacancy-drift resistive switches. APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING, 119(1), 1-9.Springer Science and Business Media LLC. doi: 10.1007/s00339-015-9033-3.

Zhang, Y., Li, Y., Sun, Z., Li, H., Chen, Y., & Jones, A.K. (2015). Read Performance: The Newest Barrier in Scaled STT-RAM. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 23(6), 1170-1174.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TVLSI.2014.2326797.

Zhang, Y., Yan, B., Kang, W., Cheng, Y., Klein, J.O.Zhang, Y., Chen, Y., & Zhao, W. (2015). Compact Model of Subvolume MTJ and Its Design Application at Nanoscale Technology Nodes. IEEE TRANSACTIONS ON ELECTRON DEVICES, 62(6), 2048-2055.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TED.2015.2414721.

Chen, L., Li, C., Huang, T., Ahmad, H.G., & Chen, Y. (2014). A phenomenological memristor model for short-term/long-term memory. PHYSICS LETTERS A, 378(40), 2924-2930.Elsevier BV. doi: 10.1016/j.physleta.2014.08.018.

Chen, L., Li, C., Huang, T., Chen, Y., & Wang, X. (2014). Memristor crossbar-based unsupervised image learning. NEURAL COMPUTING & APPLICATIONS, 25(2), 393-400.Springer Science and Business Media LLC. doi: 10.1007/s00521-013-1501-0.

Chen, Y., Guo, J., & Sun, Z. (2014). CPU-GPU System Designs for High Performance Cloud Computing. In High Performance Cloud Auditing and Applications. 9781461432968, (pp. 283-299).Springer New York. doi: 10.1007/978-1-4614-3296-8_11.

Chen, Y., Li, H., & Sun, Z. (2014). Spintronic Memristor as Interface Between DNA and Solid State Devices. In Memristors and Memristive Systems. 9781461490685, (pp. 281-298).Springer New York. doi: 10.1007/978-1-4614-9068-5_9.

Eken, E., Zhang, Y., Wen, W., Joshi, R., Li, H., & Chen, Y. (2014). A Novel Self-Reference Technique for STT-RAM Read and Write Reliability Enhancement. IEEE Transactions on Magnetics, 50(11), 1-4.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tmag.2014.2323196.

Hu, M., Li, H., Chen, Y., Wu, Q., Rose, G.S., & Linderman, R.W. (2014). Memristor Crossbar-Based Neuromorphic Computing System: A Case Study. IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS, 25(10), 1864-1878.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TNNLS.2013.2296777.

Kai, B., Yi-ran, C., Hui, X., Wei, Y., & Qi-you, X. (2014). NAND flash service lifetime estimate with recovery effect and retention time relaxation. JOURNAL OF CENTRAL SOUTH UNIVERSITY, 21(8), 3205-3213.Springer Science and Business Media LLC. doi: 10.1007/s11771-014-2292-x.

Nixon, K.W., Chen, Y., Mao, Z.H., & Li, K. (2014). User Classification and Authentication for Mobile Device Based on Gesture Recognition. In Advances in Information Security. 55, (pp. 125-135).Springer New York. doi: 10.1007/978-1-4614-7597-2_8.

Sun, G., Dong, X., Chen, Y., & Xie, Y. (2014). An Energy-Efficient 3D Stacked STT-RAM Cache Architecture for CMPs. In Emerging Memory Technologies. 9781441995513, (pp. 145-167).Springer New York. doi: 10.1007/978-1-4419-9551-3_6.

Sun, G., Joo, Y., Chen, Y., Chen, Y., & Xie, Y. (2014). A Hybrid Solid-State Storage Architecture for the Performance, Energy Consumption, and Lifetime Improvement. In Emerging Memory Technologies. 9781441995513, (pp. 51-77).Springer New York. doi: 10.1007/978-1-4419-9551-3_3.

Wen, W., Zhang, Y., Chen, Y., Wang, Y., & Xie, Y. (2014). PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 33(11), 1644-1656.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2014.2351581.

Zhang, Y., Wen, W., & Chen, Y. (2014). Asymmetry in STT-RAM Cell Operations. In Emerging Memory Technologies. 9781441995513, (pp. 117-144).Springer New York. doi: 10.1007/978-1-4419-9551-3_5.

Chen, L., Li, C., Huang, T., Chen, Y., Wen, S., & Qi, J. (2013). A synapse memristor model with forgetting effect. PHYSICS LETTERS A, 377(45-48), 3260-3265.Elsevier BV. doi: 10.1016/j.physleta.2013.10.024.

Chen, Y., Wong, W.F., Li, H., Koh, C.K., Zhang, Y., & Wen, W. (2013). On-Chip Caches Built on Multilevel Spin-Transfer Torque RAM Cells and Its Optimizations. ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 9(2), 1-22.Association for Computing Machinery (ACM). doi: 10.1145/2463585.2463592.

Li, Y., Zhang, Y., LI, H., Chen, Y., & Jones, A.K. (2013). C1C. ACM Transactions on Architecture and Code Optimization, 10(4), 1-22.Association for Computing Machinery (ACM). doi: 10.1145/2541228.2555308.

Miao Hu, Hai Li, Yiran Chen, Qing Wu, & Rose, G.S. (2013). BSB training scheme implementation on memristor-based circuit. 2013 IEEE Symposium on Computational Intelligence for Security and Defense Applications (CISDA), 9, (pp. 80-87).IEEE. doi: 10.1109/cisda.2013.6595431.

Wen, S., Bao, G., Zeng, Z., Chen, Y., & Huang, T. (2013). Global exponential synchronization of memristor-based recurrent neural networks with time-varying delays. Neural Netw, 48, 195-203.Elsevier BV. doi: 10.1016/j.neunet.2013.10.001.

Wen, S., Zeng, Z., Huang, T., & Chen, Y. (2013). Passivity analysis of memristor-based recurrent neural networks with time-varying delays. Journal of the Franklin Institute, 350(8), 2354-2370.Elsevier BV. doi: 10.1016/j.jfranklin.2013.05.026.

Wen, S., Zeng, Z., Huang, T., & Chen, Y. (2013). Fuzzy modeling and synchronization of different memristor-based chaotic circuits. Physics Letters A, 377(34-36), 2016-2021.Elsevier BV. doi: 10.1016/j.physleta.2013.05.046.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., & Li, H. (2013). Common-Source-Line Array: An Area Efficient Memory Architecture for Bipolar Nonvolatile Devices. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 18(4), 1-18.Association for Computing Machinery (ACM). doi: 10.1145/2500459.

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., & Zhang, T. (2012). A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 47(2), 560-573.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/JSSC.2011.2170778.

Li, Y., Zhang, Y., Chen, Y., & Jones, A.K. (2012). Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration. IEEE Embedded Systems Letters, 4(4), 82-85.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/les.2012.2216253.

Sun, Z., Chen, X., Zhang, Y., Li, H., & Chen, Y. (2012). Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder. ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 8(2), 1-16.Association for Computing Machinery (ACM). doi: 10.1145/2180878.2180885.

Sun, Z., Li, H., Chen, Y., & Wang, X. (2012). Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 20(11), 2020-2030.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TVLSI.2011.2166282.

Zhang, Y., Wen, W., & Chen, Y. (2012). The Prospect of STT-RAM Scaling From Readability Perspective. IEEE Transactions on Magnetics, 48(11), 3035-3038.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tmag.2012.2203589.

ZHANG, Y., WEN, W., & CHEN, Y. (2012). STT-RAM CELL DESIGN CONSIDERING MTJ ASYMMETRIC SWITCHING. SPIN, 02(03), 1240007.World Scientific Pub Co Pte Lt. doi: 10.1142/s2010324712400073.

Chen, Y., Wong, W.F., Li, H., & Koh, C.K. (2011). Processor caches built using multi-level spin-transfer torque RAM cells. IEEE/ACM International Symposium on Low Power Electronics and Design, 73-78.IEEE. doi: 10.1109/islped.2011.5993610.

Dong, X., Wu, X., Xie, Y., Chen, Y., & Li, H. (2011). Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation. IET COMPUTERS AND DIGITAL TECHNIQUES, 5(3), 213-220.Institution of Engineering and Technology (IET). doi: 10.1049/iet-cdt.2009.0091.

Hu, M., Li, H.H., Chen, Y., & Wang, X. (2011). Spintronic Memristor: Compact Model and Statistical Analysis. Journal of Low Power Electronics, 7(2), 234-244.American Scientific Publishers. doi: 10.1166/jolpe.2011.1131.

Li, H., Wang, X., Ong, Z.L., Wong, W.F., Zhang, Y., Wang, P., & Chen, Y. (2011). Performance, Power, and Reliability Tradeoffs of STT-RAM Cell Subject to Architecture-Level Requirement. IEEE TRANSACTIONS ON MAGNETICS, 47(10), 2356-2359.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TMAG.2011.2159262.

Wang, P., Wang, X., Zhang, Y., Li, H., Levitan, S.P., & Chen, Y. (2011). Nonpersistent Errors Optimization in Spin-MOS Logic and Storage Circuitry. IEEE TRANSACTIONS ON MAGNETICS, 47(10), 3860-3863.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TMAG.2011.2153838.

Xu, W., Sun, H., Wang, X., Chen, Y., & Zhang, T. (2011). Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM). IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(3), 483-493.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tvlsi.2009.2035509.

Zhang, Y., Wang, X., Li, H., & Chen, Y. (2011). STT-RAM Cell Optimization Considering MTJ and CMOS Variations. IEEE TRANSACTIONS ON MAGNETICS, 47(10), 2962-2965.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TMAG.2011.2158810.

Zhu, W., Li, H., Chen, Y., & Wang, X. (2011). Current switching in MgO-based magnetic tunneling junctions. IEEE Transactions on Magnetics, 47(1 PART 2), 156-160. doi: 10.1109/TMAG.2010.2085441.

Chen, Y., & Li, H. (2010). Patents Relevant to Cross-Point Memory Array. Recent Patents on Electrical Engineeringe, 3(2), 114-124.Bentham Science Publishers Ltd. doi: 10.2174/1874476111003020114.

Chen, Y., Li, H., Chen, C.K., Roy, K., Li, J., & Sun, G. (2010). Variable-Latency Adder (VL-Adder): New Arithmetic Circuit Design Practice for Low Power and NBTI Tolerance. IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 18(11), 1621-1624.

Chen, Y., Li, H., Koh, C.K., Sun, G., Li, J., Xie, Y., & Roy, K. (2010). Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(11), 1621-1624.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tvlsi.2009.2026280.

Chen, Y., Wang, X., Li, H., Xi, H., Yan, Y., & Zhu, W. (2010). Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(12), 1724-1734.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tvlsi.2009.2032192.

Wang, X., & Chen, Y. (2010). Patents Relevant to Spintronic Memristor. Recent Patents on Electrical Engineeringe, 3(1), 10-18.Bentham Science Publishers Ltd. doi: 10.2174/1874476111003010010.

Xi, H., Stricklin, J., Li, H., Chen, Y., Wang, X., Zheng, Y., Gao, Z., & Tang, M.X. (2010). Spin Transfer Torque Memory with Thermal Assist Mechanism: A Case Study. IEEE Transaction on Magnetics (TMAG), 46(3), 860-865.

Xi, H., Stricklin, J., Li, H., Chen, Y., Wang, X., Zheng, Y., Gao, Z., & Tang, M.X. (2010). Spin Transfer Torque Memory With Thermal Assist Mechanism: A Case Study. IEEE Transactions on Magnetics, 46(3), 860-865.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tmag.2009.2033674.

Xiaobin Wang, Yiran Chen, Ying Gu, & Hai Li. (2010). Spintronic Memristor Temperature Sensor. IEEE Electron Device Letters, 31(1), 20-22.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/led.2009.2035643.

Xu, W., Zhang, T., & Chen, Y. (2010). Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(1), 66-74.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tvlsi.2008.2007735.

Yiran Chen, Wei Tian, Hai Li, Xiaobin Wang, & Wenzhong Zhu. (2010). PCMO Device With High Switching Stability. IEEE Electron Device Letters, 31(8), 866-868.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/led.2010.2050457.

Koh, C.K., Wong, W.F., Chen, Y., & Li, H. (2009). Tolerating Process Variations in Large, Set Associative Caches: The Buddy Cache. ACM Transactions on Architecture and Code Optimization (TACO), 6(8), 34 pages.

Koh, C.K., Wong, W.F., Chen, Y., & Li, H. (2009). Tolerating process variations in large, set-associative caches. ACM Transactions on Architecture and Code Optimization, 6(2), 1-34.Association for Computing Machinery (ACM). doi: 10.1145/1543753.1543757.

Xi, H., Wang, X., Chen, Y., & Ryan, P. (2009). Ordering of Magnetic Nanoparticles in Bilayer Structures. Journal of Physics D: Applied Physics, 42(015006).

Xi, H., Wang, X., Chen, Y., & Ryan, P.J. (2009). Ordering of magnetic nanoparticles in bilayer structures. Journal of Physics D: Applied Physics, 42(1), 015006.IOP Publishing. doi: 10.1088/0022-3727/42/1/015006.

Xiaobin Wang, Yiran Chen, Haiwen Xi, Hai Li, & Dimitrov, D. (2009). Spintronic Memristor Through Spin-Torque-Induced Magnetization Motion. IEEE Electron Device Letters, 30(3), 294-297.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/led.2008.2012270.

Yiran Chen, Hai Li, Roy, K., & Cheng-Kok Koh. (2009). Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(12), 1749-1752.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tvlsi.2008.2007843.

Wang, X., Chen, Y., Li, H., Liu, H., & Dimitrov, D. (2008). Spin Torque Random Access Memory down to 22nm Technology. IEEE Transaction on Magnetics (TMAG), 44(11), 2479-2482.

Xiaobin Wang, Yiran Chen, Hai Li, Dimitrov, D., & Liu, H. (2008). Spin Torque Random Access Memory Down to 22 nm Technology. In GD-03. IEEE Transactions on Magnetics, 44, (pp. 2479-2482).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tmag.2008.2002386.

Yiran Chen, Roy, K., & Cheng-Kok Koh. (2005). Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(1), 75-85.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tvlsi.2004.840404.

Hai Li, Bhunia, S., Yiran Chen, Roy, K., & Vijaykumar, T.N. (2004). DCG: deterministic clock-gating for low-power microprocessor design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(3), 245-254.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tvlsi.2004.824307.

Chen, Y., Zhang, L., & Fan, C. (2002). Beat Phenomena and Its Suppression in Cascaded Gain-clamped EDFA. Chinese Journal of Laser, 29(3), 243-249.

Chen, Y., Zhang, L., & Fan, C. (2001). Beat Phenomena and Its Suppression in Cascaded Gain-clamped EDFA. IEEE Proceeding of Optoelectronics, 148(3), 6/2001.

Cheng, H.P., Shen, J., Yang, H., Wu, Q., Li, H., & Chen, Y. (2019). AdverQuil. In Proceedings of the 24th Asia and South Pacific Design Automation Conference, 9, (pp. 518-525).ACM. doi: 10.1145/3287624.3288753.

Fan, Z., Li, Z., Li, B., Chen, Y., & Li, H. (2019). RED: A ReRAM-based Deconvolution Accelerator. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), (pp. 1763-1768).IEEE. doi: 10.23919/date.2019.8715103.

Liu, X., Yang, H., Liu, Z., Song, L., Li, H., & Chen, Y. (2019). DPatch: An adversarial patch attack on object detectors. In CEUR Workshop Proceedings, 2301.

Min, C., Mao, J., Li, H., & Chen, Y. (2019). NeuralHMC. In Proceedings of the 24th Asia and South Pacific Design Automation Conference, (pp. 394-399).ACM. doi: 10.1145/3287624.3287642.

Song, L., Mao, J., Zhuo, Y., Qian, X., Li, H., & Chen, Y. (2019). HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array. In 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), (pp. 56-68).IEEE. doi: 10.1109/hpca.2019.00027.

Yang, H., Zhang, J., Cheng, H.P., Wang, W., Chen, Y., & Li, H. (2019). Bamboo: Ball-shape data augmentation against adversarial attacks from all directions. In CEUR Workshop Proceedings, 2301.

Chen, F., Li, Z., Kang, W., Zhao, W., Li, H., & Chen, Y. (2018). Process variation aware data management for magnetic skyrmions racetrack memory. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 54, (pp. 221-226).IEEE. doi: 10.1109/aspdac.2018.8297309.

Chen, F., Song, L., & Chen, Y. (2018). ReGAN: A pipelined ReRAM-based accelerator for generative adversarial networks. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018-January, (pp. 178-183).IEEE. doi: 10.1109/aspdac.2018.8297302.

Eken, E., Bayram, I., Li, H.H., & Chen, Y. (2018). Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018-January, (pp. 375-380).IEEE. doi: 10.1109/aspdac.2018.8297352.

Gauen, K., Dailey, R., Lu, Y.H., Park, E., Liu, W., Berg, A.C., & Chen, Y. (2018). Three years of low-power image recognition challenge: Introduction to special session. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp, (pp. 700-703).IEEE. doi: 10.23919/date.2018.8342099.

Ji, H., Song, L., Jiang, L., Li, H., & Chen, Y. (2018). ReCom: An efficient resistive accelerator for compressed deep neural networks. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018-January, (pp. 237-240).IEEE. doi: 10.23919/date.2018.8342009.

Jia, X., Yang, J., Wang, Z., Chen, Y., Li, H.H., & Zhao, W. (2018). Spintronics based stochastic computing for efficient Bayesian inference system. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018-January, (pp. 580-585).IEEE. doi: 10.1109/aspdac.2018.8297385.

Jiang, H., Yamada, K., Ren, Z., Kwok, T., Luo, F., Yang, Q., Zhang, X., Yang, J.J., Xia, Q., Chen, Y., Li, H., Wu, Q., & Barnell, M. (2018). Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array. In 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018-May, (pp. 1-4).IEEE. doi: 10.1109/iscas.2018.8351276.

Li, B., Chen, F., Kang, W., Zhao, W., Chen, Y., & Li, H. (2018). Design and Data Management for Magnetic Racetrack Memory. In 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018-May, (pp. 1-4).IEEE. doi: 10.1109/iscas.2018.8351681.

Li, B., Song, L., Chen, F., Qian, X., Chen, Y., & Li, H.H. (2018). ReRAM-based accelerator for deep learning. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018-January, (pp. 815-820).IEEE. doi: 10.23919/date.2018.8342118.

Li, B., Wen, W., Mao, J., Li, S., Chen, Y., & Li, H. (2018). Running sparse and low-precision neural network: When algorithm meets hardware. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 15, (pp. 534-539).IEEE. doi: 10.1109/aspdac.2018.8297378.

Liu, X., Wen, W., Qian, X., Li, H., & Chen, Y. (2018). Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018-January, (pp. 141-146).IEEE. doi: 10.1109/aspdac.2018.8297296.

Nixon, K.W., Mao, J., Shen, J., Yang, H., Li, H.H., & Chen, Y. (2018). SPN dash. In Proceedings of the International Conference on Computer-Aided Design, 7254, (pp. 1-6).ACM. doi: 10.1145/3240765.3240851.

Song, C., Cheng, H.P., Yang, H., Li, S., Wu, C., Wu, Q., Chen, Y., & Li, H. (2018). MAT: A Multi-strength Adversarial Training Method to Mitigate Adversarial Attacks. In 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018-July, (pp. 476-481).IEEE. doi: 10.1109/isvlsi.2018.00092.

Song, L., Zhuo, Y., Qian, X., Li, H., & Chen, Y. (2018). GraphR: Accelerating Graph Processing Using ReRAM. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018-February, (pp. 531-543).IEEE. doi: 10.1109/hpca.2018.00052.

Wang, P., Li, S., Sun, G., Wang, X., Chen, Y., Li, H., Cong, J., Xiao, N., & Zhang, T. (2018). RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 39, (pp. 518-530).IEEE. doi: 10.1109/hpca.2018.00051.

Xie, Z., Huang, Y.H., Fang, G.Q., Ren, H., Fang, S.Y., Chen, Y., & Corporation, N. (2018). RouteNet. In Proceedings of the International Conference on Computer-Aided Design.ACM. doi: 10.1145/3240765.3240843.

Yan, B., Chen, F., Zhang, Y., Song, C., Li, H., & Chen, Y. (2018). Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 25, (pp. 109-112).IEEE. doi: 10.23919/date.2018.8341988.

Yu, S., Liu, C., Wen, W., & Chen, Y. (2018). Special session on reliability and vulnerability of neuromorphic computing systems. In 2018 IEEE 36th VLSI Test Symposium (VTS), 2018-April, (p. 1).IEEE. doi: 10.1109/vts.2018.8368633.

Broyde, L., Nixon, K., Chen, X., Li, H., & Chen, Y. (2017). MobiCore: An adaptive hybrid approach for power-efficient CPU management on Android devices. In 2017 30th IEEE International System-on-Chip Conference (SOCC), 2, (pp. 221-226).IEEE. doi: 10.1109/socc.2017.8226044.

Chen, L., Li, J., Chen, Y., Deng, Q., Shen, J., Liang, X., & Jiang, L. (2017). Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, (pp. 19-24).IEEE. doi: 10.23919/date.2017.7926952.

Chen, L., Liu, Z., Li, C., Wu, J., Chen, J., & Chen, Y. (2017). Behaviors of multi-dimensional forgetting memristor models. In IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, 18, (pp. 7417-7421).IEEE. doi: 10.1109/iecon.2017.8217299.

Chen, W.H., & Chen, Y. (2017). An ensemble approach to activity recognition based on binary sensor readings. In 2017 IEEE 19th International Conference on e-Health Networking, Applications and Services (Healthcom), 11, (pp. 1-5).IEEE. doi: 10.1109/healthcom.2017.8210816.

Cheng, H.P., Wen, W., Wu, C., Li, S., Li, H.H., & Chen, Y. (2017). Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, (pp. 139-144).IEEE. doi: 10.23919/date.2017.7926972.

Hassan, A.M., Li, H.H., & Chen, Y. (2017). Hardware implementation of echo state networks using memristor double crossbar arrays. In 2017 International Joint Conference on Neural Networks (IJCNN), 26, (pp. 2171-2177).IEEE. doi: 10.1109/ijcnn.2017.7966118.

Hassan, A.M., Yang, C., Liu, C., Li, H.H., & Chen, Y. (2017). Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, (pp. 776-781).IEEE. doi: 10.23919/date.2017.7927094.

Li, S., Wen, W., Wang, Y., Han, S., Chen, Y., & Li, H. (2017). An FPGA Design Framework for CNN Sparsification and Acceleration. In 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), (p. 28).IEEE. doi: 10.1109/fccm.2017.21.

Li, Z., Liu, C., Li, H., & Chen, Y. (2017). Neuromorphic Hardware Acceleration Enabled by Emerging Technologies. International Symposium on Integrated Circuits (ISIC).Singapore. doi: 10.1007/978-3-319-54840-1_10.

Mao, J., Chen, X., Nixon, K.W., Krieger, C., & Chen, Y. (2017). MoDNN: Local distributed mobile computing system for Deep Neural Network. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, (pp. 1396-1401).IEEE. doi: 10.23919/date.2017.7927211.

Mao, J., Qin, Z., Xu, Z., Nixon, K.W., Chen, X., Li, H., & Chen, Y. (2017). AdaLearner: An adaptive distributed mobile learning system for neural networks. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), abs 1511 4561, (pp. 291-296).IEEE. doi: 10.1109/iccad.2017.8203791.

Mao, J., Yang, Z., Wen, W., Wu, C., Song, L., Nixon, K.W., Chen, X., Li, H., & Chen, Y. (2017). MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017-November, (pp. 751-756).IEEE. doi: 10.1109/iccad.2017.8203852.

Min, C., Guo, J., Li, H., & Chen, Y. (2017). Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer. In 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), (pp. 764-769).IEEE. doi: 10.1109/aspdac.2017.7858416.

Pan, C., Xie, M., Liu, Y., Wang, Y., Xue, C.J., Wang, Y., Chen, Y., & Hu, J. (2017). A lightweight progress maximization scheduler for non-volatile processor under unstable energy harvesting. In Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, 2284(5), (pp. 101-110).ACM. doi: 10.1145/3078633.3081038.

Qin, Z., Xu, Z., Dong, Q., Chen, Y., & Chen, X. (2017). VoCaM: Visualization oriented convolutional neural network acceleration on mobile system: Invited paper. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1512, (pp. 835-840).IEEE. doi: 10.1109/iccad.2017.8203864.

Song, C., Liu, B., Wen, W., Li, H., & Chen, Y. (2017). A quantization-aware regularized learning method in multilevel memristor-based neuromorphic computing system. In 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA), (pp. 1-6).IEEE. doi: 10.1109/nvmsa.2017.8064465.

Song, L., Qian, X., Li, H., & Chen, Y. (2017). PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), (pp. 541-552).IEEE. doi: 10.1109/hpca.2017.55.

Wen, W., Xu, C., Wu, C., Wang, Y., Chen, Y., & Li, H. (2017). Coordinating Filters for Faster Deep Neural Networks. In 2017 IEEE International Conference on Computer Vision (ICCV), 2, (pp. 658-666).IEEE. doi: 10.1109/iccv.2017.78.

Wen, W., Xu, C., Yan, F., Wu, C., Wang, Y., Chen, Y., & Li, H. (2017). TernGrad: Ternary gradients to reduce communication in distributed deep learning. In Advances in Neural Information Processing Systems, 2017-December, (pp. 1510-1520).

Wu, C., Wen, W., Afzal, T., Zhang, Y., Chen, Y., & Li, H. (2017). A Compact DNN: Approaching GoogLeNet-Level Accuracy of Classification and Domain Adaptation. In 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2017-January, (pp. 761-770).IEEE. doi: 10.1109/cvpr.2017.88.

Yan, B., Liu, C., Liu, X., Chen, Y., & Li, H. (2017). Understanding the trade-offs of device, circuit and application in ReRAM-based neuromorphic computing systems. In 2017 IEEE International Electron Devices Meeting (IEDM), (pp. 11.4.1-11.4.4).IEEE. doi: 10.1109/iedm.2017.8268371.

Yan, B., Yang, J., Wu, Q., Chen, Y., & Li, H. (2017). A closed-loop design to enhance weight stability of memristor based neural network chips. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 453, (pp. 541-548).IEEE. doi: 10.1109/iccad.2017.8203824.

Yin, S., Kadetotad, D., Yan, B., Song, C., Chen, Y., Chakrabarti, C., & Seo, J.S. (2017). Low-power neuromorphic speech recognition engine with coarse-grain sparsity. In 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), (pp. 111-114).IEEE. doi: 10.1109/aspdac.2017.7858305.

Bayram, I., Eken, E., Kline, D., Parshook, N., Chen, Y., & Jones, A.K. (2016). Modeling STT-RAM fabrication cost and impacts in NVSim. In 2016 Seventh International Green and Sustainable Computing Conference (IGSC), 13, (pp. 1-8).IEEE. doi: 10.1109/igcc.2016.7892599.

Bayram, I., Eken, E., Wang, X., Sun, X., Ma, T.P., & Chen, Y. (2016). Adaptive refreshing and read voltage control scheme for FeDRAM. In 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016-July, (pp. 1154-1157).IEEE. doi: 10.1109/iscas.2016.7527450.

Chakraborty, S., Joshi, S., Xia, Q., Li, H., Chen, Y., Jiang, H., Wu, Q., Barnell, M., & Yang, J.J. (2016). Built-in selectors self-assembled into memristors. In 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 32, (pp. 181-184).IEEE. doi: 10.1109/iscas.2016.7527200.

Chen, X., Khoshavi, N., Zhou, J., Huang, D., DeMara, R.F., Wang, J., Wen, W., & Chen, Y. (2016). AOS. In Proceedings of the 53rd Annual Design Automation Conference, 05-09-June-2016.ACM. doi: 10.1145/2897937.2897987.

Chen, X., Mao, J., Gao, J., Nixon, K.W., & Chen, Y. (2016). MORPh. In Proceedings of the 53rd Annual Design Automation Conference, 05-09-June-2016, (pp. 1-6).ACM. doi: 10.1145/2897937.2898047.

Chen, X., Mao, J., Nixon, K.W., & Chen, Y. (2016). MORPh. In Proceedings of the 27th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, (pp. 7-11).ACM. doi: 10.1145/2990299.2990302.

Chen, X., Nixon, K.W., & Chen, Y. (2016). Practical power consumption analysis with current smartphones. In 2016 29th IEEE International System-on-Chip Conference (SOCC), 0, (pp. 333-337).IEEE. doi: 10.1109/socc.2016.7905505.

Cheng, H.P., Wen, W., Song, C., Liu, B., Li, H., & Chen, Y. (2016). Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss. In Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016, (pp. 185-190). doi: 10.1145/2950067.2950096.

Dallal, A.H., Chen, Y., Weber, D., Mao, Z.H.Dallal, A.H., Yiran Chen, Weber, D., Zhi-Hong Mao, Weber, D., Mao, Z.H., Chen, Y.Dallal, A.H. (2016). Dictionary learning for sparse representation and classification of neural spikes. In Conf Proc IEEE Eng Med Biol Soc, 2016, (pp. 3486-3489).IEEE.United States. doi: 10.1109/EMBC.2016.7591479.

Eken, E., Bayram, I., Zhang, Y., Yan, B., Wu, W., Li, H.H., & Chen, Y. (2016). Spin-Hall Assisted STT-RAM Design and Discussion. In Proceedings of the 18th System Level Interconnect Prediction Workshop, 7, (pp. 1-4).ACM. doi: 10.1145/2947357.2947360.

Eken, E., Song, L., Bayram, I., Xu, C., Wen, W., Xie, Y., & Chen, Y. (2016). NVSim-VX s. In Proceedings of the 53rd Annual Design Automation Conference, 05-09-June-2016, (pp. 1-6).ACM. doi: 10.1145/2897937.2898053.

Guo, J., Min, C., Cai, T., & Chen, Y. (2016). A design to reduce write amplification in object-based NAND flash devices. In Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 8, (pp. 1-10).ACM. doi: 10.1145/2968456.2968465.

Guo, J., Min, C., Cai, T., Li, H., & Chen, Y. (2016). Objnandsim: object-based NAND flash device simulator. In 2016 5th Non-Volatile Memory Systems and Applications Symposium (NVMSA), (pp. 1-6).IEEE. doi: 10.1109/nvmsa.2016.7547179.

Jiang, H., Zhu, W., Luo, F., Bai, K., Liu, C., Zhang, X., Yang, J.J., Xia, Q., Chen, Y., & Wu, Q. (2016). Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing. In 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 345, (pp. 930-933).IEEE. doi: 10.1109/iscas.2016.7527394.

Li, S., Liu, X., Mao, M., Li, H.H., Chen, Y., Li, B., & Wang, Y. (2016). Heterogeneous systems with reconfigurable neuromorphic computing accelerators. In 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016-July, (pp. 125-128).IEEE. doi: 10.1109/iscas.2016.7527186.

Li, S., Wang, Y., Wen, W., Wang, Y., Chen, Y., & Li, H. (2016). A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel. In Proceedings of the 35th International Conference on Computer-Aided Design, 07-10-November-2016, (pp. 1-6).ACM. doi: 10.1145/2966986.2966987.

Li, Z., Bi, X., Li, H.H., Chen, Y., Qin, J., Guo, P., Kong, W., Zhan, W., Han, X., Zhang, H., Wang, L., Wu, G., & Wu, H. (2016). Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ. In Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 23, (pp. 4-9).ACM. doi: 10.1145/2934583.2934611.

Liu, B., Yang, C., Li, H., Chen, Y., Wu, Q., & Barnell, M. (2016). Security of neuromorphic systems: Challenges and solutions. In 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016-July, (pp. 1326-1329).IEEE. doi: 10.1109/iscas.2016.7527493.

Liu, C., Chen, Y., & Li, H. (2016). Neural processor design enabled by memristor technology. In 2016 IEEE International Conference on Rebooting Computing (ICRC), (pp. 1-4).IEEE. doi: 10.1109/icrc.2016.7738693.

Mao, M., Wen, W., Liu, X., Hu, J., Wang, D., Chen, Y., & Li, H. (2016). TEMP. In Proceedings of the 53rd Annual Design Automation Conference, 05-09-June-2016, (pp. 1-6).ACM. doi: 10.1145/2897937.2898103.

Nixon, K.W., Chen, X., & Chen, Y. (2016). Scope - quality retaining display rendering workload scaling based on user-smartphone distance. In Proceedings of the 35th International Conference on Computer-Aided Design, 1, (pp. 1-6).ACM. doi: 10.1145/2966986.2967073.

Nixon, K.W., Xiang Chen, & Yiran Chen. (2016). Footfall - GPS polling scheduler for power saving on wearable devices. In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 29, (pp. 563-568).IEEE. doi: 10.1109/aspdac.2016.7428071.

Nixon, K.W., Xiang Chen, Mao, Z.H., & Yiran Chen. (2016). SlowMo - enhancing mobile gesture-based authentication schemes via sampling rate optimization. In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28-January-2016, (pp. 462-467).IEEE. doi: 10.1109/aspdac.2016.7428055.

Song, C., Liu, B., Liu, C., Li, H., & Chen, Y. (2016). Design techniques of eNVM-enabled neuromorphic computing systems. In 2016 IEEE 34th International Conference on Computer Design (ICCD), (pp. 674-677).IEEE. doi: 10.1109/iccd.2016.7753356.

Wang, X., Mao, M., Eken, E., Wen, W., Li, H., & Chen, Y. (2016). Sliding Basket: An Adaptive ECC Scheme for Runtime Write Failure Suppression of STT-RAM Cache*. In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), (pp. 762-767).Research Publishing Services. doi: 10.3850/9783981537079_0419.

Wen, W., Mao, M., Li, H., Chen, Y., Pei, Y., & Ge, N. (2016). A Holistic Tri-region MLC STT-RAM Design with Combined Performance, Energy, and Reliability Optimizations. In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), (pp. 1285-1290).Research Publishing Services. doi: 10.3850/9783981537079_0917.

Wen, W., Wu, C., Wang, Y., Chen, Y., & Li, H. (2016). Learning structured sparsity in deep neural networks. In Advances in Neural Information Processing Systems, (pp. 2082-2090).

Wen, W., Wu, C., Wang, Y., Nixon, K., Wu, Q., Barnell, M., Li, H., & Chen, Y. (2016). A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip. In Proceedings of the 53rd Annual Design Automation Conference, 05-09-June-2016, (pp. 1-6).ACM. doi: 10.1145/2897937.2897968.

Wu, C., Cheng, H.P., Li, S., Li, H.H., & Chen, Y. (2016). ApesNet. In Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, (pp. 2-8).ACM. doi: 10.1145/2993452.2994306.

Wu, C.R., Wen, W., Ho, T.Y., & Chen, Y. (2016). Thermal optimization for memristor-based hybrid neuromorphic computing systems. In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28-January-2016, (pp. 274-279).IEEE. doi: 10.1109/aspdac.2016.7428023.

Yan, B., Li, Z., Chen, Y., & Li, H. (2016). RAM and TCAM designs by using STT-MRAM. In 2016 16th Non-Volatile Memory Technology Symposium (NVMTS), 3 e, (pp. 1-5).IEEE. doi: 10.1109/nvmts.2016.7781514.

Yan, B., Mahmoud, A.M., Yang, J.J., Wu, Q., Chen, Y., & Li, H.H. (2016). A neuromorphic ASIC design using one-selector-one-memristor crossbar. In 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 345, (pp. 1390-1393).IEEE. doi: 10.1109/iscas.2016.7527509.

Yang, C., Liu, B., Li, H., Chen, Y., Wen, W., Barnell, M., Wu, Q., & Rajendran, J. (2016). Security of neuromorphic computing. In Proceedings of the 35th International Conference on Computer-Aided Design, 07-10-November-2016.ACM. doi: 10.1145/2966986.2967074.

Yang, C., Liu, B., Wang, Y., Chen, Y., Li, H., Zhang, X., & Sun, G. (2016). The Applications of NVM Technology in Hardware Security. In Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 18-20-May-2016, (pp. 311-316).ACM. doi: 10.1145/2902961.2903043.

Yang, C., Wu, C., Li, H., Chen, Y., Barnell, M., & Wu, Q. (2016). Security challenges in smart surveillance systems and the solutions based on emerging nano-devices. In Proceedings of the 35th International Conference on Computer-Aided Design, 07-10-November-2016, (pp. 1-6).ACM. doi: 10.1145/2966986.2980092.

Zhang, X., Guangyu Sun, Zhang, Y., Chen, Y., Hai Li, Wujie Wen, & Jia Di. (2016). A novel PUF based on cell error rate distribution of STT-RAM. In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28-January-2016, (pp. 342-347).IEEE. doi: 10.1109/aspdac.2016.7428035.

Chen, L., Li, C., Huang, T., Wen, S., & Chen, Y. (2015). Memristor Crossbar Array for Image Storing. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 9377 LNCS, (pp. 166-173).Springer International Publishing. doi: 10.1007/978-3-319-25393-0_19.

Chen, X., Chen, Y., & Xue, C.J. (2015). DaTuM. In Proceedings of the 52nd Annual Design Automation Conference, 2015-July, (pp. 1-6).ACM. doi: 10.1145/2744769.2744814.

Eken, E., Zhang, Y., Yan, B., Wu, W., Li, H., & Chen, Y. (2015). Spin-hall assisted STT-RAM design and discussion. In 2015 IEEE Magnetics Conference (INTERMAG), (p. 1).IEEE. doi: 10.1109/intmag.2015.7156644.

Gu, S., Sha, E.H.M., Zhuge, Q., Chen, Y., & Hu, J. (2015). Area and performance co-optimization for domain wall memory in application-specific embedded systems. In Proceedings of the 52nd Annual Design Automation Conference, 2015-June, (pp. 1-6).ACM. doi: 10.1145/2744769.2744800.

Guo, J., Wen, W., Hu, J., Wang, D., Li, H., & Chen, Y. (2015). FlexLevel. In Proceedings of the 52nd Annual Design Automation Conference, 58, (pp. 1-6).ACM. doi: 10.1145/2744769.2744843.

Li, H., Liu, B., Liu, X., Mao, M., Chen, Y., Wu, Q., & Qiu, Q. (2015). The applications of memristor devices in next-generation cortical processor designs. In 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015-July, (pp. 17-20).IEEE. doi: 10.1109/iscas.2015.7168559.

Li, H.H., Liu, C., Yan, B., Yang, C., Song, L., Li, Z., Chen, Y., Zhu, W., Wu, Q., & Jiang, H. (2015). Spiking-based matrix computation by leveraging memristor crossbar array. In 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications (CISDA), (pp. 1-4).IEEE. doi: 10.1109/cisda.2015.7208626.

Li, Q., He, Y., Li, J., Shi, L., Chen, Y., & Xue, C.J. (2015). Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache. In IEEE TRANSACTIONS ON COMPUTERS, 64(8), (pp. 2169-2181).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2014.2360527.

Li, Z., Yan, B., Yang, L., Zhao, W., Chen, Y., & Li, H. (2015). A new self-reference sensing scheme for TLC MRAM. In 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015-July, (pp. 593-596).IEEE. doi: 10.1109/iscas.2015.7168703.

Liu, B., Li, H., Chen, Y., Li, X., Wu, Q., & Huang, T. (2015). Vortex. In Proceedings of the 52nd Annual Design Automation Conference, 2015-July.ACM. doi: 10.1145/2744769.2744930.

Liu, B., Liu, X., Liu, C., Wen, W., Meng, M., Li, H., & Chen, Y. (2015). Hardware acceleration for neuromorphic computing: An evolving view. In 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), (pp. 1-4).IEEE. doi: 10.1109/nvmts.2015.7457496.

Liu, B., Wen, W., Chen, Y., Li, X., Wu, C.R., & Ho, T.Y. (2015). EDA Challenges for Memristor-Crossbar based Neuromorphic Computing. In Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 11, (pp. 185-188).ACM. doi: 10.1145/2742060.2743754.

Liu, B., Wu, C., Li, H., Chen, Y., Wu, Q., Barnell, M., & Qiu, Q. (2015). Cloning your mind. In Proceedings of the 52nd Annual Design Automation Conference, 2015-July, (pp. 1-5).ACM. doi: 10.1145/2744769.2747915.

Liu, C., Yan, B., Yang, C., Song, L., Li, Z., Liu, B., Chen, Y., Li, H., Wu, Q., & Jiang, H. (2015). A spiking neuromorphic design with resistive crossbar. In Proceedings of the 52nd Annual Design Automation Conference, 2015-July.ACM. doi: 10.1145/2744769.2744783.

Liu, X., Mao, M., Bi, X., Li, H., & Chen, Y. (2015). An efficient STT-RAM-based register file in GPU architectures. In The 20th Asia and South Pacific Design Automation Conference, 31, (pp. 490-495).IEEE. doi: 10.1109/aspdac.2015.7059054.

Liu, X., Mao, M., Liu, B., Li, H., Chen, Y., Li, B., Wang, Y., Jiang, H., Barnell, M., Wu, Q., & Yang, J. (2015). RENO. In Proceedings of the 52nd Annual Design Automation Conference, 2015-July.ACM. doi: 10.1145/2744769.2744900.

Mao, M., Hu, J., Chen, Y., & Li, H. (2015). VWS. In Proceedings of the 52nd Annual Design Automation Conference, 2015-July, (pp. 1-6).ACM. doi: 10.1145/2744769.2744931.

Mimi Xie, Chen Pan, Jingtong Hu, Yang, C., & Chen, Y. (2015). Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units. In The 20th Asia and South Pacific Design Automation Conference, (pp. 316-321).IEEE. doi: 10.1109/aspdac.2015.7059024.

Tang, T., Xia, L., Li, B., Luo, R., Chen, Y., Wang, Y., & Yang, H. (2015). Spiking Neural Network with RRAM: Can We Use It for Real-World Application?. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015-April, (pp. 860-865).IEEE Conference Publications. doi: 10.7873/date.2015.1085.

Wen, W., Wu, C.R., Hu, X., Liu, B., Ho, T.Y., Li, X., & Chen, Y. (2015). An EDA framework for large scale hybrid neuromorphic computing systems. In Proceedings of the 52nd Annual Design Automation Conference, 2012, (pp. 1-6).ACM. doi: 10.1145/2744769.2744795.

Yan, B., Zhang, Y., Eken, E., Wen, W., Zhao, W., & Chen, Y. (2015). Recent progresses of STT memory design and applications. In 2015 IEEE 11th International Conference on ASIC (ASICON), (pp. 1-4).IEEE. doi: 10.1109/asicon.2015.7517038.

Zhang, X., Sun, G., Zhang, C., Zhang, W., Liang, Y., Wang, T., Chen, Y., & Di, J. (2015). Fork path. In Proceedings of the 48th International Symposium on Microarchitecture, 05-09-December-2015, (pp. 102-114).ACM. doi: 10.1145/2830772.2830787.

Zhang, Y., Yan, B., Wu, W., Li, H., & Chen, Y. (2015). Giant Spin Hall Effect (GSHE) Logic Design for Low Power Application. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015-April, (pp. 1000-1005).IEEE Conference Publications. doi: 10.7873/date.2015.1118.

Bayram, I., & Chen, Y. (2014). NV-TCAM: Alternative interests and practices in NVM designs. In 2014 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), 18, (pp. 1-6).IEEE. doi: 10.1109/nvmsa.2014.6927206.

Chen, L., Li, C., Huang, T., He, X., Li, H., & Chen, Y. (2014). STDP learning rule based on memristor with STDP property. In 2014 International Joint Conference on Neural Networks (IJCNN), 12, (pp. 1-6).IEEE. doi: 10.1109/ijcnn.2014.6889506.

Chen, X., Chen, Y., Dong, M., & Zhang, C. (2014). Demystifying Energy Usage in Smartphones. In Proceedings of the 51st Annual Design Automation Conference, (pp. 1-5).ACM. doi: 10.1145/2593069.2596676.

Danghui Wang, Jie Guo, Kai Bu, & Yiran Chen. (2014). Reduction of data prevention cost and improvement of reliability in MLC NAND flash storage system. In 2014 International Conference on Computing, Networking and Communications (ICNC), 1, (pp. 259-263).IEEE. doi: 10.1109/iccnc.2014.6785342.

Eken, E., Zhang, Y., Wen, W., Joshi, R., Li, H., & Chen, Y. (2014). A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. In Proceedings of the 51st Annual Design Automation Conference, (pp. 1-6).ACM. doi: 10.1145/2593069.2593075.

Guo, J., Chen, Z., Wang, D., Shao, Z., & Chen, Y. (2014). DPA: A data pattern aware error prevention technique for NAND flash lifetime extension. In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), (pp. 592-597).IEEE. doi: 10.1109/aspdac.2014.6742955.

Hu, M., Wang, Y., Qiu, Q., Chen, Y., & Li, H. (2014). The stochastic modeling of TiO<inf>2</inf> memristor and its usage in neuromorphic system design. In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 100, (pp. 831-836).IEEE. doi: 10.1109/aspdac.2014.6742993.

Hu, X., Feng, G., Li, H., Chen, Y., & Duan, S. (2014). An adjustable memristor model and its application in small-world neural networks. In 2014 International Joint Conference on Neural Networks (IJCNN), 3, (pp. 7-14).IEEE. doi: 10.1109/ijcnn.2014.6889605.

Li, B., Wang, Y., Chen, Y., Li, H.H., & Yang, H. (2014). ICE: Inline calibration for memristor crossbar-based computing engine. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, (pp. 1-4).IEEE Conference Publications. doi: 10.7873/date2014.197.

Li, B., Wang, Y., Wang, Y., Chen, Y., & Yang, H. (2014). Training itself: Mixed-signal training acceleration for memristor-based neural network. In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 25, (pp. 361-366).IEEE. doi: 10.1109/aspdac.2014.6742916.

Li, H., Liu, X., Mao, M., Chen, Y., Wu, Q., & Bamell, M. (2014). Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper). In 2014 International Symposium on Integrated Circuits (ISIC), 1, (pp. 124-127).IEEE. doi: 10.1109/isicir.2014.7029530.

Li, X., Duan, S., Wang, L., Huang, T., & Chen, Y. (2014). Memristive Radial Basis Function Neural Network for Parameters Adjustment of PID Controller. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 8866, (pp. 150-158).Springer International Publishing. doi: 10.1007/978-3-319-12436-0_17.

Liu, B., Li, H., Chen, Y., Li, X., Huang, T., Wu, Q., & Barnell, M. (2014). Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems. In 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015-January(January), (pp. 63-70).IEEE. doi: 10.1109/iccad.2014.7001330.

Liu, X., Li, Y., Zhang, Y., Jones, A.K., & Chen, Y. (2014). STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 31, (pp. 355-360).IEEE. doi: 10.1109/aspdac.2014.6742915.

Mao, M., Sun, G., Li, Y., Jones, A.K., & Chen, Y. (2014). Prefetching techniques for STT-RAM based last-level cache in CMP systems. In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 31, (pp. 67-72).IEEE. doi: 10.1109/aspdac.2014.6742868.

Mao, M., Wen, W., Zhang, Y., Chen, Y., & Li, H.H. (2014). Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. In Proceedings of the 51st Annual Design Automation Conference, 31, (pp. 1-6).ACM. doi: 10.1145/2593069.2593137.

Pan, C., Xie, M., Hu, J., Chen, Y., & Yang, C. (2014). 3M-PCM. In Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 45, (pp. 1-10).ACM. doi: 10.1145/2656075.2656076.

Sun, M., Burke, L.E., Mao, Z.H., Chen, Y., Chen, H.C., Bai, Y., Li, Y., Li, C., & Jia, W. (2014). eButton: A Wearable Computer for Health Monitoring and Personal Assistance. In Proc Des Autom Conf, 2014, (pp. 1-6).ACM.United States. doi: 10.1145/2593069.2596678.

Wang, Y., Li, B., Luo, R., Chen, Y., Xu, N., & Yang, H. (2014). Energy efficient neural networks for big data analytics. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, (pp. 1-2).IEEE Conference Publications. doi: 10.7873/date2014.358.

Wen, W., Zhang, Y., Mao, M., & Chen, Y. (2014). STT-RAM reliability enhancement through ECC and access scheme optimization. In The 18th IEEE International Symposium on Consumer Electronics (ISCE 2014), (pp. 1-2).IEEE. doi: 10.1109/isce.2014.6884324.

Wen, W., Zhang, Y., Mao, M., & Chen, Y. (2014). State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System. In Proceedings of the 51st Annual Design Automation Conference, 103, (pp. 1-6).ACM. doi: 10.1145/2593069.2593220.

Wu, Q., Liu, B., Chen, Y., Li, H., Chen, Q., & Qiu, Q. (2014). Bio-inspired computing with resistive memories &#x2014; models, architectures and applications. In 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1, (pp. 834-837).IEEE. doi: 10.1109/iscas.2014.6865265.

Xiaoxiao Liu, Mengjie Mao, Hai Li, Yiran Chen, Hao Jiang, Yang, J.J., Qing Wu, & Barnell, M. (2014). A heterogeneous computing system with memristor-based neuromorphic accelerators. In 2014 IEEE High Performance Extreme Computing Conference (HPEC), (pp. 1-6).IEEE. doi: 10.1109/hpec.2014.7040986.

Zhang, C., Sun, G., Li, P., Wang, T., Niu, D., & Chen, Y. (2014). SBAC. In Proceedings of the 2014 international symposium on Low power electronics and design, 31, (pp. 345-350).ACM. doi: 10.1145/2627369.2627611.

Chen, X., Chen, Y., Ma, Z., & Fernandes, F.C.A. (2013). How is energy consumed in smartphone display applications?. In Proceedings of the 14th Workshop on Mobile Computing Systems and Applications.ACM. doi: 10.1145/2444776.2444781.

Guo, J., Wen, W., Li, Y.Z., Li, S., Li, H., & Chen, Y. (2013). DA-RAID-5: A Disturb Aware Data Protection Technique for NAND Flash Storage Systems. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, (pp. 380-385).IEEE Conference Publications. doi: 10.7873/date.2013.087.

Guo, J., Yang, J., Zhang, Y., & Chen, Y. (2013). Low Cost Power Failure Protection for MLC NAND Flash Storage Systems with PRAM/DRAM Hybrid Buffer. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, (pp. 859-864).IEEE Conference Publications. doi: 10.7873/date.2013.181.

Jones, A.K., Chen, Y., Collinge, W.O., Xu, H., Schaefer, L.A., Landis, A.E., & Bilec, M.M. (2013). Considering fabrication in sustainable computing. In 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 206-210).IEEE. doi: 10.1109/iccad.2013.6691120.

Li, B., Shan, Y., Hu, M., Wang, Y., Chen, Y., & Yang, H. (2013). Memristor-based approximated computation. In International Symposium on Low Power Electronics and Design (ISLPED), 12, (pp. 242-247).IEEE. doi: 10.1109/islped.2013.6629302.

Li, J., Shi, L., Li, Q., Xue, C.J., Chen, Y., & Xu, Y. (2013). Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM. Poster session presented at the meeting of Design Automation and Test in Europe.

Li, J., Shi, L., Li, Q., Xue, C.J., Chen, Y., Xu, Y., & Wang, W. (2013). Low-Energy Volatile STT-RAM Cache Design Using Cache-Coherence-Enabled Adaptive Refresh. In ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 19(1), (pp. 1-23).Association for Computing Machinery (ACM). doi: 10.1145/2534393.

Li, Y., Zhang, Y., Li, H., Chen, Y., & Jones, A.K. (2013). C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache. In ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 10(4), (pp. 1-22).Association for Computing Machinery (ACM). doi: 10.1145/2555289.2555308.

Liu, B., Hu, M., Li, H., Mao, Z.H., Chen, Y., Huang, T., & Zhang, W. (2013). Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine. In Proceedings of the 50th Annual Design Automation Conference, (pp. 1-6).ACM. doi: 10.1145/2463209.2488741.

Mao, M., Li, H.H., Jones, A.K., & Chen, Y. (2013). Coordinating prefetching and STT-RAM based last-level cache management for multicore systems. In Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI, 31, (pp. 55-60).ACM. doi: 10.1145/2483028.2483060.

Nixon, K.W., Xiang Chen, Zhi-Hong Mao, Yiran Chen, & Kang Li. (2013). Mobile user classification and authorization based on gesture usage recognition. In 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 56, (pp. 384-389).IEEE. doi: 10.1109/aspdac.2013.6509626.

Qingan Li, Jianhua Li, Liang Shi, Xue, C.J., Yiran Chen, & Yanxiang He. (2013). Compiler-assisted refresh minimization for volatile STT-RAM cache. In 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), (pp. 273-278).IEEE. doi: 10.1109/aspdac.2013.6509608.

Wen, W., Mao, M., Zhu, X., Kang, S.H., Wang, D., & Chen, Y. (2013). CD-ECC: Content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors. In 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 1-8).IEEE. doi: 10.1109/iccad.2013.6691090.

Wujie Wen, Yaojun Zhang, Lu Zhang, & Yiran Chen. (2013). Loadsa: A yield-driven top-down design method for STT-RAM array. In 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), (pp. 291-296).IEEE. doi: 10.1109/aspdac.2013.6509611.

Yaojun Zhang, Lu Zhang, & Yiran Chen. (2013). MLC STT-RAM design considering probabilistic and asymmetric MTJ switching. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), (pp. 113-116).IEEE. doi: 10.1109/iscas.2013.6571795.

Zhang, L., Chen, Z., Yang, J.J., Wysocki, B., McDonald, N., & Chen, Y. (2013). A compact modeling of TiO2-TiO2-x memristor. In APPLIED PHYSICS LETTERS, 102(15).AIP Publishing. doi: 10.1063/1.4802206.

Zhang, Y., Bayram, I., Wang, Y., Li, H., & Chen, Y. (2013). ADAMS: Asymmetric differential STT-RAM cell structure for reliable and high-performance applications. In 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 336, (pp. 9-16).IEEE. doi: 10.1109/iccad.2013.6691091.

Zhao, M., Hao Zhang, Chen, X., Chen, Y., & Xue, C.J. (2013). Online OLED dynamic voltage scaling for video streaming applications on mobile devices. 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). doi: 10.1109/codes-isss.2013.6658996.

Bi, X., Zhang, C., Li, H., Chen, Y., & Pino, R.E. (2012). Spintronic memristor based temperature sensor design with CMOS current reference. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 1301-1306).

Chen, X., Liu, B., Chen, Y., Zhao, M., Xue, C.J., & Guo, X. (2012). Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays. In Proceedings of the International Conference on Computer-Aided Design, (pp. 516-522).ACM. doi: 10.1145/2429384.2429493.

Chen, X., Zheng, J., Chen, Y., Zhao, M., & Xue, C.J. (2012). Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices. In Proceedings of the 49th Annual Design Automation Conference, 2, (pp. 1000-1005).ACM. doi: 10.1145/2228360.2228540.

Chen, Y., Chen, X., Zhao, M., & Xue, C.J. (2012). Mobile devices user-The subscriber and also the publisher of real-time OLED display power management plan. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, (pp. 687-690).

Chen, Y., Zhang, Y., & Wang, P. (2012). Probabilistic design in spintronic memory and logic circuit. In 17th Asia and South Pacific Design Automation Conference, (pp. 323-328).IEEE. doi: 10.1109/aspdac.2012.6164967.

Hu, M., Li, H., Wu, Q., Rose, G.S., & Chen, Y. (2012). Memristor crossbar based hardware realization of BSB recall function. In The 2012 International Joint Conference on Neural Networks (IJCNN), (pp. 1-7).IEEE. doi: 10.1109/ijcnn.2012.6252563.

Li, Y., Chen, Y., & Jones, A.K. (2012). A software approach for combating asymmetries of non-volatile memories. In Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, 2, (pp. 191-196).ACM. doi: 10.1145/2333660.2333708.

Liu, B., Chen, Y., Wysocki, B., & Huang, T. (2012). The Circuit Realization of a Neuromorphic Computing System with Memristor-Based Synapse Design. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 7663 LNCS(PART 1), (pp. 357-365).Springer Berlin Heidelberg. doi: 10.1007/978-3-642-34475-6_43.

Pino, R.E., Li, H.H., Chen, Y., Hu, M., & Liu, B. (2012). Statistical memristor modeling and case study in neuromorphic computing. In Proceedings of the 49th Annual Design Automation Conference, 7275, (pp. 585-590).ACM. doi: 10.1145/2228360.2228466.

Shao, Z., Liu, Y., Chen, Y., & Li, T. (2012). Utilizing PCM for Energy Optimization in Embedded Systems. In 2012 IEEE Computer Society Annual Symposium on VLSI, (pp. 398-403).IEEE. doi: 10.1109/isvlsi.2012.81.

Sun, G., Zhang, Y., Wang, Y., & Chen, Y. (2012). Improving energy efficiency of write-asymmetric memories by log style write. In Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, (pp. 173-178).ACM. doi: 10.1145/2333660.2333705.

Wang, P., Zhang, W., Joshi, R., Kanj, R., & Chen, Y. (2012). A thermal and process variation aware MTJ switching model and its applications in soft error analysis. In Proceedings of the International Conference on Computer-Aided Design, (pp. 720-727).ACM. doi: 10.1145/2429384.2429541.

Wen, W., Zhang, Y., Chen, Y., Wang, Y., & Xie, Y. (2012). PS3-RAM. In Proceedings of the 49th Annual Design Automation Conference, 22, (pp. 1191-1196).ACM. doi: 10.1145/2228360.2228580.

Xiang Chen, Jian Zeng, Yiran Chen, Wei Zhang, & Hai Li. (2012). Fine-grained dynamic voltage scaling on OLED display. In 17th Asia and South Pacific Design Automation Conference, (pp. 807-812).IEEE. doi: 10.1109/aspdac.2012.6165066.

Zhang, Y., Wang, X., Li, Y., Jones, A.K., & Chen, Y. (2012). Asymmetry of MTJ switching and its implication to STT-RAM designs. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 1313-1318).

Zhang, Y., Zhang, L., Wen, W., Sun, G., & Chen, Y. (2012). Multi-level cell STT-RAM: Is it realistic or just a dream?. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, (pp. 526-532).

Zhao, B., Yang, J., Zhang, Y., Chen, Y., & Li, H. (2012). Architecting a common-source-line array for bipolar non-volatile memory devices. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 1451-1454).

Chen, Y., & Li, H. (2011). Emerging sensing techniques for emerging memories. In 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), (pp. 204-210).IEEE. doi: 10.1109/aspdac.2011.5722185.

Chen, Y.C., Li, H., Chen, Y., & Pino, R.E. (2011). 3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 583-586).

Hu, M., Li, H., Chen, Y., Wang, X., & Pino, R.E. (2011). Geometry variations analysis of TiO<inf>2</inf> thin-film and spintronic memristors. In 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), (pp. 25-30).IEEE. doi: 10.1109/aspdac.2011.5722193.

Wang, P., Chen, X., Chen, Y., Li, H., Kang, S., Zhu, X., & Wu, W. (2011). A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis. In 2011 IEEE Custom Integrated Circuits Conference (CICC), (pp. 1-4).IEEE. doi: 10.1109/cicc.2011.6055392.

Xue, C.J., Zhang, Y., Chen, Y., Sun, G., Yang, J.J., & Li, H. (2011). Emerging non-volatile memories. In Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (pp. 325-334).ACM. doi: 10.1145/2039370.2039420.

Zhang, Y., Wang, X., & Chen, Y. (2011). STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view. In 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 100, (pp. 471-477).IEEE. doi: 10.1109/iccad.2011.6105370.

Zhou, P., Zhao, B., Zhang, Y., Yang, J., & Chen, Y. (2011). MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement. In 2011 International Conference on Parallel Architectures and Compilation Techniques, (pp. 207-208).IEEE. doi: 10.1109/pact.2011.29.

Che, Y., Li, H., & Wang, X. (2010). Spintronic devices: From memory to memristor. In 2010 International Conference on Communications, Circuits and Systems (ICCCAS), (pp. 811-816).IEEE. doi: 10.1109/icccas.2010.5581868.

Chen, Y., Li, H., Wang, X., & Park, J. (2010). Applications of TMR devices in solid state circuits and systems. In 2010 International SoC Design Conference, (pp. 252-255).IEEE. doi: 10.1109/socdc.2010.5682923.

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., & Zhang, T. (2010). Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. In Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, (pp. 1-6).ACM. doi: 10.1145/1840845.1840847.

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., & Zhang, T. (2010). A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM). In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 148-153).

Chen, Y., Wang, X., Sun, Z., & Li, H. (2010). The application of spintronic devices in magnetic bio-sensing. In 2nd Asia Symposium on Quality Electronic Design (ASQED), 159, (pp. 230-234).IEEE. doi: 10.1109/asqed.2010.5548244.

Chen, Y., Wang, X., Zhu, W., Li, H., Sun, Z., Sun, G., & Xie, Y. (2010). Access scheme of Multi-Level Cell Spin-Transfer Torque Random Access Memory and its optimization. In 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, (pp. 1109-1112).IEEE. doi: 10.1109/mwscas.2010.5548848.

Chen, Y., Wei Tian, Li, H., Xiaobin Wang, & Wenzhong Zhu. (2010). Scalability of PCMO-based resistive switch device in DSM technologies. In 2010 11th International Symposium on Quality Electronic Design (ISQED), 89, (pp. 327-332).IEEE. doi: 10.1109/isqed.2010.5450447.

Hai Li, & Yiran Chen. (2010). Emerging non-volatile memory technologies: From materials, to device, circuit, and architecture. In 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 159, (pp. 1-4).IEEE. doi: 10.1109/mwscas.2010.5548590.

Niu, D., Chen, Y., & Xie, Y. (2010). Low-power dual-element memristor based memory design. In Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, (pp. 25-30).ACM. doi: 10.1145/1840845.1840851.

Niu, D., Chen, Y., Xu, C., & Xie, Y. (2010). Impact of process variations on emerging memristor. In Proceedings of the 47th Design Automation Conference, (pp. 877-882).ACM. doi: 10.1145/1837274.1837495.

Sun, G., Joo, Y., Chen, Y., Niu, D., Xie, Y., Chen, Y., & Li, H. (2010). A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. In HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, 43, (pp. 1-12).IEEE. doi: 10.1109/hpca.2010.5416650.

Sun, Z., Li, H., Chen, Y., & Wang, X. (2010). Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement. In 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 432-437).IEEE. doi: 10.1109/iccad.2010.5653720.

Wang, X., & Chen, Y. (2010). Spintronic memristor devices and application. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 667-672).

Chen, Y., & Wang, X. (2009). Compact modeling and corner analysis of spintronic memristor. In 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 159, (pp. 7-12).IEEE. doi: 10.1109/nanoarch.2009.5226363.

Koh, C.K., Wong, W.F., Chen, Y., & Li, H. (2009). The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. In 2009 IEEE International Conference on Computer Design, 39, (pp. 268-274).IEEE. doi: 10.1109/iccd.2009.5413145.

Li, H., Xi, H., Chen, Y., Stricklin, J., Wang, X., & Zhang, T. (2009). Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration. In 2009 IEEE Computer Society Annual Symposium on VLSI, 100, (pp. 217-222).IEEE. doi: 10.1109/isvlsi.2009.17.

Sun, G., Dong, X., Xie, Y., Li, J., & Chen, Y. (2009). A novel architecture of the 3D stacked MRAM L2 cache for CMPs. In 2009 IEEE 15th International Symposium on High Performance Computer Architecture, 11, (pp. 239-249).IEEE. doi: 10.1109/hpca.2009.4798259.

Xu, W., Chen, Y., Wang, X., & Zhang, T. (2009). Improving STT MRAM storage density through smaller-than-worst-case transistor sizing. In Proceedings of the 46th Annual Design Automation Conference, 19, (pp. 87-90).ACM. doi: 10.1145/1629911.1629936.

Chen, Y., Wang, X., Li, H., Liu, H., & Dimitrov, D.V. (2008). Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM). In 9th International Symposium on Quality Electronic Design (isqed 2008), (pp. 684-690).IEEE. doi: 10.1109/isqed.2008.4479820.

Dong, X., Wu, X., Sun, G., Xie, Y., Li, H., & Chen, Y. (2008). Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In Proceedings - Design Automation Conference, (pp. 554-559). doi: 10.1109/DAC.2008.4555878.

Wei Xu, Tong Zhang, & Yiran Chen. (2008). Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin. In 2008 IEEE International Symposium on Circuits and Systems, (pp. 1898-1901).IEEE. doi: 10.1109/iscas.2008.4541813.

Chen, Y., Li, H., Li, J., & Koh, C.K. (2007). Variable-latency adder (VL-adder). In Proceedings of the 2007 international symposium on Low power electronics and design, (pp. 195-200).ACM. doi: 10.1145/1283780.1283822.

Li, H., Koh, C.K., Balakrishnan, V., & Chen, Y. (2007). Statistical Timing Analysis Considering Spatial Correlations. In 8th International Symposium on Quality Electronic Design (ISQED'07), (pp. 102-107).IEEE. doi: 10.1109/isqed.2007.149.

Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, & Hai Li. (2007). VOSCH: Voltage scaled cache hierarchies. In 2007 25th International Conference on Computer Design, (pp. 496-503).IEEE. doi: 10.1109/iccd.2007.4601944.

Li, H., Chen, Y., Roy, K., & Koh, C.K. (2006). SAVS: A self-adaptive variable supply-voltage technique for process- Tolerant and power-efficient multi-issue superscalar processor design. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006, (pp. 158-163).

Chen, Y., Li, H., Roy, K., & Koh, C.K. (2005). Cascaded carry-select adder (C2 SA): A new structure for low-power CSA design. In Proceedings of the International Symposium on Low Power Electronics and Design, (pp. 115-118).

Dongku Kang, Yiran Chen, & Roy, K. (2005). Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. In Sixth International Symposium on Quality of Electronic Design (ISQED'05), 13, (pp. 48-53).IEEE. doi: 10.1109/isqed.2005.97.

Lam, W.C.D., Jain, J., Koh, C.K., Balakrishnan, V., & Chen, Y. (2005). Statistical based link insertion for robust clock network design. In ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., 2005, (pp. 588-591).IEEE. doi: 10.1109/iccad.2005.1560134.

Yiran Chen, Hai Li, Roy, K., & Cheng-Kok Koh. (2005). Gated decap: gate leakage control of on-chip decoupling capacitors in scaled technologies. In Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005., 32 4, (pp. 770-773).IEEE. doi: 10.1109/cicc.2005.1568783.

Chen, Y., Roy, K., & Koh, C.K. (2004). Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, (pp. 894-899).

Hai Li, Bhunia, S., Chen, Y., Vijaykumar, T.N., & Roy, K. (2003). Deterministic clock gating for microprocessor power reduction. In The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings., 12, (pp. 113-122).IEEE Comput. Soc. doi: 10.1109/hpca.2003.1183529.

Yiran Chen, Roy, K., & Cheng-Kok Koh. (2003). Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. In Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03., q3, (pp. 229-234).ACM. doi: 10.1109/lpe.2003.1231867.

Chen, Y., Balakrishnan, V., Koh, C.K., & Roy, K. (2002). Model reduction in the time-domain using Laguerre polynomials and Krylov methods. In Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, (pp. 931-935).IEEE Comput. Soc. doi: 10.1109/date.2002.998411.

Research interests

Embedded systems and mobile...
Emerging memory and sensing...
Mobile technology and human-machine...
Nano-electronic devices (silicon...