about

(2009) Best Paper Nominee, The 15th International Symposium on High-Performance Computer Architecture.

(2008) NSF Faculty Early Career Development Award (CAREER).

(2007 - 2013) Best Paper, ISLPED 2013; ICCD, processor architecture track.

(2003 - 2004) Regent's Faculty Fellowship / Faculty Development Award.

Ph.D., Computer Science, University of Arizona, 2002

M.S., Computer Science, University of Pittsburgh, 1999

M.A., Applied Mathematics, Worcester Polytechnic Institute, 1997

B.S., Computer Science, Nanjing University, 1995

Cui, J., Zhang, Y., Shi, L., Xue, C.J., Yang, J., Liu, W., & Yang, L.T. (2020). Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems. JOURNAL OF SYSTEMS ARCHITECTURE, 103, 101685.Elsevier BV. doi: 10.1016/j.sysarc.2019.101685.

Deng, Q., Zhang, Y., Zhao, Z., Zhang, S., Zhang, M., & Yang, J. (2020). FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(10), 2396-2409.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2019.2946808.

Gao, C., Shi, L., Li, Q., Liu, K., Xue, C.J., Yang, J., & Zhang, Y. (2020). Aging Capacitor Supported Cache Management Scheme for Solid-State Drives. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(10), 2230-2239.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2019.2949541.

Gao, C., Shi, L., Liu, K., Xue, C.J., Yang, J., & Zhang, Y. (2020). Boosting the Performance of SSDs via Fully Exploiting the Plane Level Parallelism. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 31(9), 2185-2200.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TPDS.2020.2987894.

Li, C., Zigerelli, A., Yang, J., Zhang, Y., Ma, S., & Guo, Y. (2020). A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(1), 75-87.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2018.2883906.

Wen, W., Zhao, L., Zhang, Y., & Yang, J. (2020). Exploiting In-Memory Data Patterns for Performance Improvement on Crossbar Resistive Memory. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(10), 2347-2360.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2019.2940685.

Li, C., Sun, Y., Jin, L., Xu, L., Cao, Z., Fan, P., Kaeli, D., Ma, S., Guo, Y., & Yang, J. (2019). Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems. IEEE COMPUTER ARCHITECTURE LETTERS, 18(2), 157-160.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2019.2955119.

Pan, J., Ding, S., Wu, D., Yang, S., & Yang, J. (2019). Exploring behavioural intentions toward smart healthcare services among medical practitioners: a technology transfer perspective. INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH, 57(18), 5801-5820.Informa UK Limited. doi: 10.1080/00207543.2018.1550272.

Cui, J., Zhang, Y., Shi, L., Xue, C.J., Wu, W., & Yang, J. (2018). ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 37(10), 1957-1970.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2017.2782765.

Cui, J., Zhang, Y., Wu, W., Yang, J., Wang, Y., & Huang, J. (2018). DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 37(8), 1546-1559.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2017.2766156.

Wang, C., Wei, Q., Wu, L., Wang, S., Chen, C., Xiao, X., Yang, J., Xue, M., & Yang, Y. (2018). Persisting RB-Tree into NVM in a Consistency Perspective. ACM Transactions on Storage, 14(1), 1-27.Association for Computing Machinery (ACM). doi: 10.1145/3177915.

Wang, C., Wei, Q., Yang, J., Chen, C., Yang, Y., & Xue, M. (2018). NV-Dedup: High-Performance Inline Deduplication for Non-Volatile Memory. IEEE Transactions on Computers, 67(5), 658-671.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tc.2017.2774270.

Wang, R., Mittal, S., Zhang, Y., & Yang, J. (2017). Decongest: Accelerating Super-Dense PCM Under Write Disturbance by Hot Page Remapping. IEEE COMPUTER ARCHITECTURE LETTERS, 16(2), 107-110.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2017.2675883.

Wen, W., Yang, J., & Zhang, Y. (2017). Optimizing power efficiency for 3D stacked GPU-in-memory architecture. MICROPROCESSORS AND MICROSYSTEMS, 49, 44-53.Elsevier BV. doi: 10.1016/j.micpro.2017.01.005.

Zhang, X., Zhang, Y., Childers, B.R., & Yang, J. (2017). On the Restore Time Variations of Future DRAM Memory. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 22(2), 1-24.Association for Computing Machinery (ACM). doi: 10.1145/2967609.

Wang, Z., Yang, J., Melhem, R., Childers, B., Zhang, Y., & Guo, M. (2016). Simultaneous Multikernel: Fine-Grained Sharing of GPUs. IEEE COMPUTER ARCHITECTURE LETTERS, 15(2), 113-116.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2015.2477405.

Yang, J., Wei, Q., Wang, C., Chen, C., Yong, K.L., & He, B. (2016). NV-Tree: A Consistent and Workload-Adaptive Tree Structure for Non-Volatile Memory. IEEE Transactions on Computers, 65(7), 2169-2183.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tc.2015.2479621.

Jiang, L., Zhao, B., Yang, J., & Zhang, Y. (2015). Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 20(4), 1-24.Association for Computing Machinery (ACM). doi: 10.1145/2764903.

Li, P., Luo, Y., & Yang, J. (2015). Transformer: Run-time reprogrammable heterogeneous architecture for transparent acceleration of dynamic workloads. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 86, 45-61.Elsevier BV. doi: 10.1016/j.jpdc.2015.08.002.

Wang, R., Jiang, L., Zhang, Y., & Yang, J. (2015). SD-PCM Constructing Reliable Super Dense Phase Change Memory under Write Disturbance. ACM SIGPLAN NOTICES, 50(4), 19-31.ACM. doi: 10.1145/2694344.2694352.

Wei, Q., Chen, C., Xue, M., & Yang, J. (2015). Z-MAP. ACM Transactions on Storage, 11(1), 1-33.Association for Computing Machinery (ACM). doi: 10.1145/2629663.

Xu, Y., Zhao, B., Zhang, Y., & Yang, J. (2015). Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers. ACM Transactions on Parallel Computing, 2(1), 1-23.Association for Computing Machinery (ACM). doi: 10.1145/2742349.

Zhao, B., Du, Y., Yang, J., & Zhang, Y. (2014). Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor (vol 62, pg 2252, 2013). IEEE TRANSACTIONS ON COMPUTERS, 63(2), 525-526.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2014.5.

Zhao, B., Du, Y., Yang, J., & Zhang, Y. (2014). Erratum: Process variation-aware nonuniform cache management in a 3d die-stacked multicore processor (IEEE Transactions on Computers (2013) 62:11 (2252-2265)). IEEE Transactions on Computers, 63(2), 525-526. doi: 10.1109/TC.2014.5.

Zhou, P., Zhao, B., Yang, J., & Zhang, Y. (2014). Throughput Enhancement for Phase Change Memories. IEEE TRANSACTIONS ON COMPUTERS, 63(8), 2080-2093.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2013.76.

Jiang, L., Du, Y., Zhao, B., Zhang, Y., Childers, B.R., & Yang, J. (2013). Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 10(2), 1-25.Association for Computing Machinery (ACM). doi: 10.1145/2459316.2459318.

Jiang, L., Du, Y., Zhao, B., Zhang, Y., Childers, B.R., & Yang, J. (2013). Hardware-assisted cooperative integration of wear-leveling and salvaging for phase change memory. Transactions on Architecture and Code Optimization, 10(2). doi: 10.1145/2459316.2459.

Zhao, B., Du, Y., Yang, J., & Zhang, Y. (2013). Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor. IEEE TRANSACTIONS ON COMPUTERS, 62(11), 2252-2265.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2012.129.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., & Li, H. (2013). Common-Source-Line Array: An Area Efficient Memory Architecture for Bipolar Nonvolatile Devices. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 18(4), 1-18.Association for Computing Machinery (ACM). doi: 10.1145/2500459.

Lee, B.C., Zhou, P., Yang, J., Zhang, Y., Zhao, B., Ipek, E., Mutlu, O., & Burger, D. (2010). PHASE-CHANGE TECHNOLOGY AND THE FUTURE OF MAIN MEMORY. IEEE MICRO, 30(1), 131-141.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MM.2010.24.

Xia, L., Zhu, Y., Yang, J., Ye, J., & Gu, Z. (2010). Implementing a Thermal-Aware Scheduler in Linux Kernel on a Multi-Core Processor. COMPUTER JOURNAL, 53(7), 895-903.Oxford University Press (OUP). doi: 10.1093/comjnl/bxp119.

Yang, J., Gao, L., Zhang, Y., Chrobak, M., & Lee, H.H.S. (2010). A low-cost memory remapping scheme for address bus protection. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 70(5), 443-457.Elsevier BV. doi: 10.1016/j.jpdc.2009.11.008.

Zhang, Y., Yang, J., Li, W., Wang, L., & Jin, L. (2010). An authentication scheme for locating compromised sensor nodes in WSNs. JOURNAL OF NETWORK AND COMPUTER APPLICATIONS, 33(1), 50-62.Elsevier BV. doi: 10.1016/j.jnca.2009.06.003.

Zhang, Y., Yang, J., Vu, H.T., & Wu, Y. (2010). The design and evaluation of interleaved authentication for filtering false reports in multipath routing WSNs. WIRELESS NETWORKS, 16(1), 125-140.Springer Science and Business Media LLC. doi: 10.1007/s11276-008-0119-0.

Zhou, X., Yang, J., Chrobak, M., & Zhang, Y. (2010). Performance-Aware Thermal Management via Task Scheduling. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 7(1). doi: 10.1145/1746065.1736070.

Zhou, X., Yang, J., Chrobak, M., & Zhang, Y. (2010). Performance-aware thermal management via task scheduling. ACM Transactions on Architecture and Code Optimization, 7(1), 1-31.Association for Computing Machinery (ACM). doi: 10.1145/1736065.1736070.

Zhou, X., Yang, J., Xu, Y., Zhang, Y., & Zhao, J. (2010). Thermal-Aware Task Scheduling for 3D Multicore Processors. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 21(1), 60-71.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TPDS.2009.27.

Li, W., Zhang, Y., Yang, J., & Zheng, J. (2009). Towards Update-Conscious Compilation for Energy-Efficient Code Dissemination in WSNs. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 6(4), 1-33.Association for Computing Machinery (ACM). doi: 10.1145/1596510.1596512.

Suresh, D., Agrawal, B., Yang, J., & Najjar, W. (2009). Energy-Efficient Encoding Techniques for Off-Chip Data Buses. ACM Transactions on Embedded Computing Systems, 8(2;9).

Suresh, D.C., Agrawal, B., Yang, J., & Najjar, W. (2009). Energy-Efficient Encoding Techniques for Off-Chip Data Buses. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 8(2), 1-23.Association for Computing Machinery (ACM). doi: 10.1145/1457255.1457256.

Suresh, D.C., Agrawal, B., Yang, J., & Najjar, W.A. (2009). Tunable and Energy Efficient Bus Encoding Techniques. IEEE TRANSACTIONS ON COMPUTERS, 58(8), 1049-1062.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2009.39.

Zhang, Y., Yang, J., & Gao, L. (2009). Supporting flexible streaming media protection through privacy-aware secure processors. COMPUTERS & ELECTRICAL ENGINEERING, 35(2), 286-299.Elsevier BV. doi: 10.1016/j.compeleceng.2008.06.001.

Luo, Y., Yu, J., Yang, J., & Bhuyan, L. (2007). Conserving Network Processor Power Consump-tion by Exploiting Traffic Variability. ACM Transactions on Architecture and Code Optimization, 4(1;4), 26 pages.

Luo, Y., Yu, J., Yang, J., & Bhuyan, L.N. (2007). Conserving network processor power consumption by exploiting traffic variability. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 4(1), 4.Association for Computing Machinery (ACM). doi: 10.1145/1216544.1216547.

Wu, W., Jin, L., Yang, J., Liu, P., & Tan, S. (2007). Efficient Power Modeling and Soft-ware Thermal Sensing for Runtime Temperature Monitoring. ACM Transactions on Design Automation of Electronic Systems, Special Issue on Demonstrable Software Systems and Hardware Plat-forms, 12(3;26), 29 pages.

Liu, P., Li, H., Jin, L., Wu, W., Tan, S.X.D., & Yang, J. (2006). Fast thermal simulation for runtime temperature tracking and management. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 25(12), 2882-2893.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2006.882594.

Yang, J., Gao, L., & Zhang, Y.T. (2005). Improving memory encryption performance in secure processors. IEEE TRANSACTIONS ON COMPUTERS, 54(5), 630-640.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2005.80.

Yang, J., Yu, J., & Zhang, Y.T. (2005). A low energy cache design for multimedia applications exploiting set access locality. JOURNAL OF SYSTEMS ARCHITECTURE, 51(10-11), 653-664.Elsevier BV. doi: 10.1016/j.sysarc.2005.02.003.

Zhang, C., Vahid, F., Yang, J., & Najjar, W. (2005). A way-halting cache for low-energy high-performance systems. ACM Transactions on Architecture and Code Optimization, 2(1), 34-54.Association for Computing Machinery (ACM). doi: 10.1145/1061267.1061270.

Zhang, Y., & Yang, J. (2005). Reducing I-cache Energy of Multimedia Applications through Low Cost Tag Comparison Elimination. Journal of Embedded Computing, 1(4), 461-470.

Chen, X., Luo, Y., Hsieh, H., Bhuyan, L., & Balarin, F. (2004). Assertion based verification and analysis of network processor architectures. DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, 9(3), 163-176.Springer Science and Business Media LLC. doi: 10.1007/s10617-005-1193-5.

Luo, Y., Yang, J., Bhuyan, L.N., & Zhao, L. (2004). Nepsim: A network processor simulator with a power evaluation framework. IEEE MICRO, 24(5), 34-44.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MM.2004.52.

Yang, J., Gupta, R., & Zhang, C.J. (2004). Frequent value encoding for low power data buses. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 9(3), 354-384.Association for Computing Machinery (ACM). doi: 10.1145/1013948.1013953.

Chuanjun Zhang, Vahid, F., Jun Yang, & Walid, W. (2003). A Way-Halting Cache for Low-Energy High-Performance Systems. IEEE Computer Architecture Letters, 2(1), 5.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/l-ca.2003.2.

Suresh, D.C., Yang, J., Zhang, C.J., Agrawal, B., & Najjar, W. (2003). FV-MSB: A scheme for reducing transition activity on data buses. HIGH PERFORMANCE COMPUTING - HIPC 2003, 2913, 44-54.Springer Berlin Heidelberg. doi: 10.1007/978-3-540-24596-4_6.

Yang, J., & Gupta, R. (2002). Frequent value locality and its applications. ACM Transactions on Embedded Computing Systems, 1(1), 79-105.Association for Computing Machinery (ACM). doi: 10.1145/581888.581894.

Tang, D., & Yang, J. (2000). Free Moving Boundary Model and Boundary Iteration Method for Unsteady Viscous Flow in Stenotic Elastic Tubes. SIAM Journal on Scientific Computing, 21(4), 1370-1386.

Zhang, Y., Yang, J., & Gupta, R. (2000). Frequent value locality and value-centric data cache design. ACM SIGOPS Operating Systems Review, 34(5), 150-159.Association for Computing Machinery (ACM). doi: 10.1145/384264.379235.

Zhang, Y., Yang, J., & Gupta, R. (2000). Frequent value locality and value-centric data cache design. ACM SIGPLAN Notices, 35(11), 150-159.Association for Computing Machinery (ACM). doi: 10.1145/356989.357003.

Tang, D., Yang, J., Yang, C., & Ku, D.N. (1999). A nonlinear axisymmetric model with fluid-wall interactions for steady viscous flow in stenotic elastic tubes. JOURNAL OF BIOMECHANICAL ENGINEERING-TRANSACTIONS OF THE ASME, 121(5), 494-501.ASME International. doi: 10.1115/1.2835078.

Yang, B., Chen, R., Huang, K., Yang, J., & Gao, W. (2022). Eavesdropping user credentials via GPU side channels on smartphones. In Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems.ACM. doi: 10.1145/3503222.3507757.

Ganguly, D., Melhem, R., & Yang, J. (2021). An Adaptive Framework for Oversubscription Management in CPU-GPU Unified Memory. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021-February, (pp. 1212-1217).IEEE. doi: 10.23919/date51398.2021.9473982.

Gao, C., Xin, X., Lu, Y., Zhang, Y., Yang, J., & Shu, J. (2021). ParaBit: Processing Parallel Bitwise Operations in NAND Flash Memory based SSDs. In MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, (pp. 59-70).ACM. doi: 10.1145/3466752.3480078.

Guo, Y., Zigerelli, A., Zhang, Y., & Yang, J. (2021). IVcache. In Proceedings of the 2021 on Great Lakes Symposium on VLSI, (pp. 403-408).ACM. doi: 10.1145/3453688.3461481.

Xin, X., Guo, Y., Zhang, Y., & Yang, J. (2021). SAM: Accelerating Strided Memory Accesses. In MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, (pp. 324-336).ACM. doi: 10.1145/3466752.3480091.

Ganguly, D., Zhang, Z., Yang, J., & Melhem, R. (2020). Adaptive Page Migration for Irregular Data-intensive Applications under GPU Memory Oversubscription. In 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), (pp. 451-461).IEEE. doi: 10.1109/ipdps47924.2020.00054.

Nie, S., Zhang, Y., Wu, W., & Yang, J. (2020). Layer RBER Variation Aware Read Performance Optimization for 3D Flash Memories. In 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020-July.IEEE. doi: 10.1109/dac18072.2020.9218631.

Tang, X., Zhang, Z., Xu, W., Kandemir, M.T., Melhem, R., & Yang, J. (2020). Enhancing Address Translations in Throughput Processors via Compression. In Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques, (pp. 191-204).ACM. doi: 10.1145/3410463.3414633.

Wen, W., Zhang, Y., & Yang, J. (2020). Accelerating 3D vertical resistive memories with opportunistic write latency reduction. In Proceedings of the 39th International Conference on Computer-Aided Design, 2020-November.ACM. doi: 10.1145/3400302.3415677.

Xin, X., Zhang, Y., & Yang, J. (2020). ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), (pp. 303-314).IEEE. doi: 10.1109/hpca47549.2020.00033.

Xin, X., Zhang, Y., & Yang, J. (2020). Reducing DRAM Access Latency via Helper Rows. In 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020-July.IEEE. doi: 10.1109/dac18072.2020.9218719.

Zhao, L., Zhang, Y., & Yang, J. (2020). SCA: A Secure CNN Accelerator for Both Training and Inference. In 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020-July.IEEE. doi: 10.1109/dac18072.2020.9218752.

Deng, Q., Zhang, Y., Zhang, M., & Yang, J. (2019). LAcc. In Proceedings of the 56th Annual Design Automation Conference 2019.ACM. doi: 10.1145/3316781.3317845.

Ganguly, D., Zhang, Z., Yang, J., & Melhem, R. (2019). Interplay between hardware prefetcher and page eviction policy in CPU-GPU unified virtual memory. In Proceedings of the 46th International Symposium on Computer Architecture, (pp. 224-235).ACM. doi: 10.1145/3307650.3322224.

Gao, C., Shi, L., Xue, C.J., Ji, C., Yang, J., & Zhang, Y. (2019). Parallel all the time: Plane Level Parallelism Exploration for High Performance SSDs. In 2019 35th Symposium on Mass Storage Systems and Technologies (MSST), 2019-May, (pp. 172-184).IEEE. doi: 10.1109/msst.2019.000-5.

Gao, C., Ye, M., Li, Q., Xue, C.J., Zhang, Y., Shi, L., & Yang, J. (2019). Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, (pp. 493-505).ACM. doi: 10.1145/3352460.3358323.

Li, C., Ausavarungnirun, R., Rossbach, C.J., Zhang, Y., Mutlu, O., Guo, Y., & Yang, J. (2019). A Framework for Memory Oversubscription Management in Graphics Processing Units. In Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, (pp. 49-63).ACM. doi: 10.1145/3297858.3304044.

Li, Q., Shi, L., Yang, J., Zhang, Y., & Xue, C.J. (2019). Leveraging Approximate Data for Robust Flash Storage. In Proceedings of the 56th Annual Design Automation Conference 2019.ACM. doi: 10.1145/3316781.3317848.

Liu, L., Wang, R., Zhang, Y., & Yang, J. (2019). H-ORAM. In Proceedings of the 56th Annual Design Automation Conference 2019.ACM. doi: 10.1145/3316781.3317841.

Nie, S., Zhang, Y., Wu, W., Zhang, C., & Yang, J. (2019). DIR: Dynamic Request Interleaving for Improving the Read Performance of Aged SSDs. In 2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA).IEEE. doi: 10.1109/nvmsa.2019.8863520.

Raoufi, M., Deng, Q., Zhang, Y., & Yang, J. (2019). PageCmp: Bandwidth Efficient Page Deduplication through In-memory Page Comparison. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019-July, (pp. 82-87).IEEE. doi: 10.1109/isvlsi.2019.00023.

Wen, W., Zhang, Y., & Yang, J. (2019). ReNEW: Enhancing Lifetime for ReRAM Crossbar Based Neural Network Accelerators. In 2019 IEEE 37th International Conference on Computer Design (ICCD), (pp. 487-496).IEEE. doi: 10.1109/iccd46524.2019.00074.

Xin, X., Zhang, Y., & Yang, J. (2019). ROC. In Proceedings of the 56th Annual Design Automation Conference 2019.ACM. doi: 10.1145/3316781.3317900.

Zhang, X., Wang, R., Zhang, Y., & Yang, J. (2019). Boosting chipkill capability under retention-error induced reliability emergency. In Proceedings of the 24th Asia and South Pacific Design Automation Conference, (pp. 438-443).ACM. doi: 10.1145/3287624.3287639.

Zhao, L., Deng, Q., Zhang, Y., & Yang, J. (2019). RFAcc. In Proceedings of the ACM International Conference on Supercomputing, (pp. 473-483).ACM. doi: 10.1145/3330345.3330387.

Cui, J., Zhang, Y., Huang, J., Wu, W., & Yang, J. (2018). ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDs. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018-January, (pp. 1247-1252).IEEE. doi: 10.23919/date.2018.8342206.

Deng, Q., Jiang, L., Zhang, Y., Zhang, M., & Yang, J. (2018). DrAcc. In Proceedings of the 55th Annual Design Automation Conference, Part F137710.ACM. doi: 10.1145/3195970.3196029.

Garrett, T., Yang, J., & Zhang, Y. (2018). Enabling Intra-Plane Parallel Block Erase in NAND Flash to Alleviate the Impact of Garbage Collection. In Proceedings of the International Symposium on Low Power Electronics and Design.ACM. doi: 10.1145/3218603.3218627.

Li, C., Zigerelli, A., Yang, J., & Guo, Y. (2018). PEP. In Proceedings of the 55th Annual Design Automation Conference, Part F137710.ACM. doi: 10.1145/3195970.3196091.

Wang, R., Zhang, Y., & Yang, J. (2018). D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted Memory. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018-February, (pp. 416-427).IEEE. doi: 10.1109/hpca.2018.00043.

Wen, W., Zhang, Y., & Yang, J. (2018). Wear leveling for crossbar resistive memory. In Proceedings of the 55th Annual Design Automation Conference, Part F137710.ACM. doi: 10.1145/3195970.3196138.

Xu, Y., Yang, J., & Melhem, R. (2018). A Process-Variation-Tolerant Method for Nanophotonic On-Chip Network. In ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 14(2), (pp. 1-23).Association for Computing Machinery (ACM). doi: 10.1145/3208073.

Chen, C., Yang, J., Wei, Q., Wang, C., & Xue, M. (2017). Optimizing File Systems with Fine-grained Metadata Journaling on Byte-addressable NVM. In ACM Transactions on Storage, 13(2), (pp. 1-25).Association for Computing Machinery (ACM). doi: 10.1145/3060147.

Deng, Q., Zhang, Y., Zhang, M., & Yang, J. (2017). Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017-November, (pp. 736-742).IEEE. doi: 10.1109/iccad.2017.8203850.

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Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Yang, J., & Li Zhao. (2009). Frequent value compression in packet-based NoC architectures. In 2009 Asia and South Pacific Design Automation Conference, (pp. 13-18).IEEE. doi: 10.1109/aspdac.2009.4796434.

Yi Xu, Yu Du, Bo Zhao, Xiuyi Zhou, Youtao Zhang, & Yang, J. (2009). A low-radix and low-diameter 3D interconnection network design. In 2009 IEEE 15th International Symposium on High Performance Computer Architecture, (pp. 30-41).IEEE. doi: 10.1109/hpca.2009.4798234.

Zhao, B., Du, Y., Zhang, Y., & Yang, J. (2009). Variation-tolerant non-uniform 3D cache management in die stacked multicore processor. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, (pp. 222-231).ACM. doi: 10.1145/1669112.1669141.

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Li, W., Zhang, Y., & Yang, J. (2006). Dynamic Authentication-Key Re-assignment for Reliable Report Delivery. In 2006 IEEE International Conference on Mobile Ad Hoc and Sensor Sysetems, 1, (pp. 467-476).IEEE. doi: 10.1109/mobhoc.2006.278587.

Weidong Shi, Fryman, J.B., Guofei Gu, Hsien Hsin S. Lee, Youtao Zhang, & Jun Yang. (2006). InfoShield: A Security Architecture for Protecting Information Usage in Memory. In The Twelfth International Symposium on High-Performance Computer Architecture, 2006., 2006, (pp. 225-234).IEEE. doi: 10.1109/hpca.2006.1598131.

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Youtao Zhang, Jim Yang, & Vu, H.T. (2006). The interleaved authentication for filtering false reports in multipath routing based sensor networks. In Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006.IEEE. doi: 10.1109/ipdps.2006.1639330.

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Jia Yu, Wei Wu, Xi Chen, Hsieh, H., Jun Yang, & Balarin, F. (2005). Assertion-Based Design Exploration of DVS in Network Processor Architectures. In Design, Automation and Test in Europe, I, (pp. 92-97).IEEE. doi: 10.1109/date.2005.69.

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Lin, Y., Zhang, Y., Li, Q., & Yang, J. (2005). Supporting efficient query processing on compressed XML files. In Proceedings of the 2005 ACM symposium on Applied computing, 1, (pp. 660-665).ACM. doi: 10.1145/1066677.1066827.

Luo, Y., Yu, J., Yang, J., & Bhuyan, L. (2005). Low power network processor design using clock gating. In Proceedings of the 42nd annual conference on Design automation - DAC '05, (pp. 712-715).ACM Press. doi: 10.1145/1065579.1065766.

Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, & Jun Yang. (2005). Fast thermal simulation for architecture level dynamic thermal management. In ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., 2005, (pp. 639-644).IEEE. doi: 10.1109/iccad.2005.1560145.

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Youtao Zhang, Lan Gao, Jun Yang, Xiangyu Zhang, & Gupta, R. (2005). SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors. In 11th International Symposium on High-Performance Computer Architecture, (pp. 352-362).IEEE. doi: 10.1109/hpca.2005.31.

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Zhang, C., Vahid, F., Yang, J., & Najjar, W. (2004). A Way-Halting Cache for Low-Energy High-Performance Systems. In Proceedings of the International Symposium on Low Power Electronics and Design, 2004-January(January), (pp. 126-131). doi: 10.1109/LPE.2004.240851.

Zhang, C., Vahid, F., Yang, J., & Najjar, W. (2004). A way-halting cache for low-energy high-performance systems. In Proceedings of the 2004 international symposium on Low power electronics and design, (pp. 126-131).ACM. doi: 10.1145/1013235.1013272.

Zhang, C., Yang, J., & Vahid, F. (2004). Low static-power frequent-value data caches. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, 1, (pp. 214-219).

Jun Yang, Youtao Zhang, & Lan Gao. (2003). Fast secure processor for inhibiting software piracy and tampering. In 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), 2003-January, (pp. 351-360).IEEE Comput. Soc. doi: 10.1109/micro.2003.1253209.

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Research interests

embedded systems
hardware security
Memory systems
Processor microarchitecture