Berman, F., Rutenbar, R., Hailpern, B., Christensen, H., Davidson, S., Estrin, D., Franklin, M., Martonosi, M., Raghavan, P., Stodden, V., & Szalay, A.S. (2018). Realizing the Potential of Data Science. COMMUNICATIONS OF THE ACM, 61(4), 67-72.Association for Computing Machinery (ACM). doi: 10.1145/3188721.
Rutenbar, R.A., Cohn, J.M., Lin, M.P.H., & Baskaya, F. (2017). Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology. In Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology. (pp. 479-500).CRC Press. doi: 10.1201/9781315215112.
Choi, J., & Rutenbar, R.A. (2016). Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform. IEEE Transactions on Circuits and Systems for Video Technology, 26(2), 385-398.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tcsvt.2015.2397198.
Kim, E.P., Choi, J., Shanbhag, N.R., & Rutenbar, R.A. (2016). Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(3), 897-908.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tvlsi.2015.2437331.
Rutenbar, R.A. (2014). DAC at 50: The Second 25 Years. IEEE Design & Test, 31(2), 32-39.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/mdat.2014.2312093.
Zhang, W., Balakrishnan, K., Li, X., Boning, D.S., Saxena, S., Strojwas, A., & Rutenbar, R.A. (2013). Efficient Spatial Pattern Analysis for Variation Decomposition via Robust Sparse Regression. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 32(7), 1072-1085.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2013.2245942.
Bourke, P.J., Yu, K., & Rutenbar, R.A. (2012). Mobile Speech Hardware: The Case for Custom Silicon. In Speech in Mobile and Pervasive Environments. (pp. 7-56).Wiley. doi: 10.1002/9781119961710.ch2.
Zhang, W., Li, X., Liu, F., Acar, E., Rutenbar, R.A., & Blanton, R.D. (2011). Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 30(12), 1814-1827.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2011.2164536.
Singhee, A., & Rutenbar, R.A. (2010). Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(11), 1763-1776.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tcad.2010.2062750.
Wang, J., Singhee, A., Rutenbar, R.A., & Calhoun, B.H. (2010). Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(12), 1908-1920.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tcad.2010.2061810.
Aktuna, M., Rutenbar, R.A., & Carley, L.R. (2009). DeviceLevel Early Floorplanning Algorithms for RF Circuits. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 494-507).IEEE. doi: 10.1109/9780470544310.ch41.
Cohn, J.M., Garrod, D.J., Rutenbar, R.A., & Carley, L.R. (2009). KOAN/ANAGRAM II: New Tools for DeviceLevel Analog Placement and Routing. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 382-394).IEEE. doi: 10.1109/9780470544310.ch31.
Gielen, G.G.E., & Rutenbar, R.A. (2009). ComputerAided Design of Analog and MixedSignal Integrated Circuits. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 3-30).IEEE. doi: 10.1109/9780470544310.ch1.
Krasnicki, M., Phelps, R., Rutenbar, R.A., & Carley, L.R. (2009). MAELSTROM: Efficient SimulationBased Synthesis for Custom Analog Cells. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 190-195).IEEE. doi: 10.1109/9780470544310.ch15.
Maulik, P.C., Carley, L.R., & Rutenbar, R.A. (2009). Integer Programming Based Topology Selection of CellLevel Analog Circuits. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 113-124).IEEE. doi: 10.1109/9780470544310.ch8.
Mitra, S., Nag, S.K., Rutenbar, R.A., & Carley, L.R. (2009). Systemlevel Routing of MixedSignal ASICs in WREN. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 471-476).IEEE. doi: 10.1109/9780470544310.ch38.
Mitra, S., Rutenbar, R.A., Carley, L.R., & Allstot, D.J. (2009). SubstrateAware MixedSignal Macrocell Placement in WRIGHT. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 461-470).IEEE. doi: 10.1109/9780470544310.ch37.
Mukherjee, T., Carley, L.R., & Rutenbar, R.A. (2009). Efficient Handling of Operating Range and Manufacturing Line Variations in Analog Cell Synthesis. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 703-717).IEEE. doi: 10.1109/9780470544310.ch59.
Ochotta, E.S., Rutenbar, R.A., & Carley, L.R. (2009). Synthesis of HighPerformance Analog Circuits in ASTRX/OBLX. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 168-189).IEEE. doi: 10.1109/9780470544310.ch14.
Phelps, R., Krasnicki, M., Rutenbar, R.A., Carley, L.R., & Hellums, J.R. (2009). Anaconda: SimulationBased Synthesis of Analog Circuits Via Stochastic Pattern Search. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 196-210).IEEE. doi: 10.1109/9780470544310.ch16.
Phelps, R., Krasnicki, M.J., Rutenbar, R.A., Carley, L.R., & Hellums, J.R. (2009). A Case Study of Synthesis for IndustrialScale Analog IP: Redesign of the Equalizer/Filter Frontend for an ADSL CODEC. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 211-216).IEEE. doi: 10.1109/9780470544310.ch17.
Rutenbar, R.A., & Cohn, J.M. (2009). Layout Tools for Analog ICs and MixedSignal SoCs: A Survey. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 365-372).IEEE. doi: 10.1109/9780470544310.ch29.
Singhee, A., & Rutenbar, R.A. (2009). Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 28(8), 1176-1189.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2009.2020721.
Singhee, A., & Rutenbar, R.A. (2009). Statistical blockade: Very fast statistical simulation and modeling of rare circuit events and its application to memory design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(1), 1176-1189.
Stanisic, B.R., Verghese, N.K., Rutenbar, R.A., Carley, L.R., & Allstot, D.J. (2009). Addressing Substrate Coupling in MixedMode IC's: Simulation and Power Distribution Synthesis. In Computer-Aided Design of Analog Integrated Circuits and Systems. (pp. 477-489).IEEE. doi: 10.1109/9780470544310.ch39.
Calhoun, B.H., Cao, Y., Li, X., Mai, K., Pileggi, L.T., Rutenbar, R.A., & Shepard, K.L. (2008). Digital circuit design challenges and opportunities in the era of nanoscale CMOS. PROCEEDINGS OF THE IEEE, 96(2), 343-365.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/JPROC.2007.911072.
Singhee, A., & Rutenbar, R.A. (2008). Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application. In Design, Automation, and Test in Europe. (pp. 235-251).Springer Netherlands. doi: 10.1007/978-1-4020-6488-3_18.
Ma, J.D., & Rutenbar, R.A. (2007). Interval-valued reduced-order statistical interconnect modeling. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 26(9), 1602-1613.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2007.895577.
Rutenbar, R.A., Gielen, G.G.E., & Roychowdhury, J. (2007). Hierarchical modeling, optimization, and synthesis for system-level analog and RF designs. PROCEEDINGS OF THE IEEE, 95(3), 640-669.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/JPROC.2006.889371.
Frehse, G., Krogh, B.H., Rutenbar, R.A., & Maler, O. (2006). Time Domain Verification of Oscillator Circuit Properties. Electronic Notes in Theoretical Computer Science, 153(3), 9-22.Elsevier BV. doi: 10.1016/j.entcs.2006.02.019.
Rutenbar, R.A., & Cohn, J.M. (2006). Layout tools for analog integrated circuits and mixed-signal systems-on-chip: A survey. In EDA for IC Implementation, Circuit Design, and Process Technology. (p. 16-1-16-17).
Gopalakrishnan, P., & Rutenbar, R.A. (2005). Direct Transistor-level Layout for Digital Blocks. 1-125.Kluwer Academic Publishers. doi: 10.1007/b117054.
Nam, G.J., Aloul, F., Sakallah, K.A., & Rutenbar, R.A. (2004). A comparative study of two Boolean formulations of FPGA detailed routing constraints. IEEE TRANSACTIONS ON COMPUTERS, 53(6), 688-696.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2004.1.
Xu, H., Rutenbar, R.A., & Sakallah, K. (2003). sub-SAT: A formulation for relaxed Boolean satisriability with applications in routing. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 22(6), 814-820.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2003.811450.
Fang, F., Chen, T.H., & Rutenbar, R.A. (2002). Lightweight floating-point arithmetic: Case study of inverse discrete cosine transform. EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING, 2002(9), 879-892.Springer Science and Business Media LLC. doi: 10.1155/S1110865702205090.
Nam, G.J., Sakallah, K.A., & Rutenbar, R.A. (2002). A new FPGA detailed routing approach via search-based Boolean satisfiability. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 21(6), 674-684.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2002.1004311.
Rutenbar, R.A., Gielen, G.G.E., & Antao, B.A. (2002). Computer-Aided Design of Analog Integrated Circuits and Systems. ix-x.IEEE. doi: 10.1109/9780470544310.
Kay, R., & Rutenbar, R.A. (2001). Wire packing - A strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 20(5), 672-679.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/43.920702.
Krasnicki, M.J., Phelps, R., Hellums, J.R., McClung, M., Rutenbar, R.A., & Carley, L.R. (2001). ASF: a practical simulation-based methodology for the synthesis of custom analog circuits. IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281), 350-357.IEEE. doi: 10.1109/iccad.2001.968646.
Leenaerts, D., Gielen, G., & Rutenbar, R.A. (2001). CAD solutions and outstanding challenges for mixed-signal and RF IC design. IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281), 270-277.IEEE. doi: 10.1109/iccad.2001.968633.
Gielen, G.G.E., & Rutenbar, R.A. (2000). Computer-aided design of analog and mixed-signal integrated circuits. PROCEEDINGS OF THE IEEE, 88(12), 1825-1852.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/5.899053.
Mukherjee, T., Carley, R., & Rutenbar, R.A. (2000). Efficient handling of operating range and manufacturing line variations in analog cell synthesis. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 19(8), 825-839.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/43.856971.
Phelps, R., Krasnicki, M., Rutenbar, R.A., Carley, L.R., & Hellums, J.R. (2000). Anaconda: Simulation-based synthesis of analog circuits via stochastic pattern search. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 19(6), 703-717.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/43.848091.
Tong, J.Y.F., Nagle, D., & Rutenbar, R.A. (2000). Reducing power by optimizing the necessary precision/range of floating-point arithmetic. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 8(3), 273-286.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/92.845894.
Aktuna, M., Rutenbar, R.A., & Carley, L.R. (1999). Device-level early floorplanning algorithms for RF circuits. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 46(3), 375-388.
Aktuna, M., Rutenbar, R.A., & Carley, L.R. (1999). Device-level early floorplanning algorithms for RF circuits. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 18(4), 375-388.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/43.752922.
Krasnicki, M., Phelps, R., Rutenbar, R.A., & Carley, L.R. (1999). MAELSTROM: Efficient simulation-based synthesis for custom analog cells. Proceedings - Design Automation Conference, 945-950.
Meier, P.C.H., Rutenbar, R.A., & Carley, L.R. (1999). Inverse polarity techniques for high-speed/low-power multipliers. Proceedings of the 1999 international symposium on Low power electronics and design - ISLPED '99, 264-266.ACM Press. doi: 10.1145/313817.313942.
Nam, G.J., Sakallah, K.A., & Rutenbar, R.A. (1999). Satisfiability-based layout revisited: Detailed routing of complex FPGAs via search-based Boolean SAT. ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA, 167-175.
Phelps, R., Krasnicki, M., Rutenbar, R.A., Carley, L.R., & Hellums, J.R. (1999). ANACONDA: robust synthesis of analog circuits via stochastic pattern search. Proceedings of the Custom Integrated Circuits Conference, 567-570.
Nag, S.K., & Rutenbar, R.A. (1998). Performance-driven simultaneous placement and routing for FPGA's. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 17(6), 499-518.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/43.703831.
Wood, R.G., & Rutenbar, R.A. (1998). FPGA routing and routability estimation via Boolean satisfiability. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 6(2), 222-231.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/92.678873.
Ochotta, E.S., Rutenbar, R.A., & Carley, L.R. (1996). Synthesis of high-performance analog circuits in ASTRX/OBLX. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 15(3), 273-294.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/43.489099.
DIRECTOR, S.W., KHOSLA, P.K., ROHRER, R.A., & RUTENBAR, R.A. (1995). REENGINEERING THE CURRICULUM - DESIGN AND ANALYSIS OF A NEW UNDERGRADUATE ELECTRICAL AND COMPUTER-ENGINEERING DEGREE AT CARNEGIE-MELLON-UNIVERSITY. PROCEEDINGS OF THE IEEE, 83(9), 1246-1269.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/5.406429.
MAULIK, P.C., CARLEY, R., & RUTENBAR, R.A. (1995). INTEGER PROGRAMMING BASED TOPOLOGY SELECTION OF CELL-LEVEL ANALOG CIRCUITS. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 14(4), 401-412.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/43.372366.
MITRA, S., RUTENBAR, R.A., CARLEY, L.R., & ALLSTOT, D.J. (1995). SUBSTRATE-AWARE MIXED-SIGNAL MACROCELL PLACEMENT IN WRIGHT. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 30(3), 269-278.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/4.364441.
Mukherjee, T., Carley, L.R., & Rutenbar, R.A. (1994). Synthesis of manufacturable analog circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 586-593.
STANISIC, B.R., VERGHESE, N.K., RUTENBAR, R.A., CARLEY, L.R., & ALLSTOT, D.J. (1994). ADDRESSING SUBSTRATE COUPLING IN MIXED-MODE ICS - SIMULATION AND POWER DISTRIBUTION SYNTHESIS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 29(3), 226-238.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/4.278344.
SETLIFF, D.E., & RUTENBAR, R.A. (1992). KNOWLEDGE REPRESENTATION AND REASONING IN A SOFTWARE SYNTHESIS ARCHITECTURE. IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, 18(6), 523-533.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/32.142874.
COHN, J.M., GARROD, D.J., RUTENBAR, R.A., & CARLEY, L.R. (1991). KOAN ANAGRAM-II - NEW TOOLS FOR DEVICE-LEVEL ANALOG PLACEMENT AND ROUTING. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 26(3), 330-342.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/4.75012.
KRAVITZ, S.A., BRYANT, R.E., & RUTENBAR, R.A. (1991). MASSIVELY PARALLEL SWITCH-LEVEL SIMULATION - A FEASIBILITY STUDY. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 10(7), 871-894.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/43.87598.
SETLIFF, D.E., & RUTENBAR, R.A. (1991). ON THE FEASIBILITY OF SYNTHESIZING CAD SOFTWARE FROM SPECIFICATIONS - GENERATING MAZE ROUTER TOOLS IN ELF. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 10(6), 783-801.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/43.137507.
HARJANI, R., RUTENBAR, R.A., & CARLEY, L.R. (1989). OASYS - A FRAMEWORK FOR ANALOG CIRCUIT SYNTHESIS. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 8(12), 1247-1266.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/43.44506.
RUTENBAR, R.A. (1989). SIMULATED ANNEALING ALGORITHMS - AN OVERVIEW. IEEE CIRCUITS & DEVICES, 5(1), 19-26.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/101.17235.
CARLEY, L.R., & RUTENBAR, R.A. (1988). HOW TO AUTOMATE ANALOG IC DESIGNS. IEEE SPECTRUM, 25(8), 26-30.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/6.7160.
RUTENBAR, R.A., & ATKINS, D.E. (1988). SYSTOLIC ROUTING HARDWARE - PERFORMANCE EVALUATION AND OPTIMIZATION. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 7(3), 397-410.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/43.3173.
CARLSON, E.C., & RUTENBAR, R.A. (1987). A SCANLINE DATA STRUCTURE PROCESSOR FOR VLSI GEOMETRY CHECKING. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 6(5), 780-794.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.1987.1270321.
KRAVITZ, S.A., & RUTENBAR, R.A. (1987). PLACEMENT BY SIMULATED ANNEALING ON A MULTIPROCESSOR. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 6(4), 534-549.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.1987.1270301.
Carlson, E.C., & Rutenbar, R.A. (1986). SCANLINE DATA STRUCTURE PROCESSOR FOR VLSI GEOMETRY CHECKING. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-6(5).
RUTENBAR, R.A., & HARJANI, R. (1986). SYNTHESIS OF ANALOG VLSI MODULES. IEEE SOFTWARE, 3(2), 58.
DIRECTOR, S.W., MALY, W., RUTENBAR, R.A., SHEN, J.P., SIEWIOREK, D.P., STROJWAS, A.J., & THOMAS, D.E. (1985). INTEGRATED CAD, CAM, AND CAT OF VLSI CIRCUITS AND SYSTEMS - THE CMU PERSPECTIVE. IEEE DESIGN & TEST OF COMPUTERS, 2(3), 87-93.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/mdt.1985.294767.
Rutenbar, R.A., Mudge, T.N., & Atkins, D.E. (1984). A Class of Cellular Architectures to Support Physical Design Automation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 3(4), 264-278.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tcad.1984.1270085.
Rutenbar, R.A., & Park, Y.E. (1981). Case study of a VLSI design project: A simple inner product machine. 1981 IEEE 5th Symposium on Computer Arithmetic (ARITH), 184-189.IEEE. doi: 10.1109/arith.1981.6159292.
Kim, S., Lee, K., Cho, W., Nam, Y., Cheon, J.H., & Rutenbar, R.A. (2020). Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme. In 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), (pp. 56-64).IEEE. doi: 10.1109/fccm48280.2020.00017.
Ko, G., Chai, Y., Donato, M., Whatmough, P.N., Tambe, T., Rutenbar, R.A., Wei, G.Y., & Brooks, D. (2020). A Scalable Bayesian Inference Accelerator for Unsupervised Learning. In 2020 IEEE Hot Chips 32 Symposium (HCS).IEEE. doi: 10.1109/hcs49909.2020.9220686.
Ko, G.G., Chai, Y., Donato, M., Whatmough, P.N., Tambe, T., Rutenbar, R.A., Brooks, D., & Wei, G.Y. (2020). A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm. In 2020 IEEE Symposium on VLSI Circuits, 2020-June.IEEE. doi: 10.1109/vlsicircuits18222.2020.9162784.
Gao, T., & Rutenbar, R.A. (2019). A Virtual Image Accelerator for Graph Cuts Inference on FPGA. In 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019-July, (p. 137).IEEE. doi: 10.1109/asap.2019.00-15.
Kim, S., & Rutenbar, R.A. (2019). An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA. In Proceedings of the 2019 on Great Lakes Symposium on VLSI, (pp. 87-92).ACM. doi: 10.1145/3299874.3318002.
Kim, S., Lee, K., Cho, W., Cheon, J.H., & Rutenbar, R.A. (2019). FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption. In 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig).IEEE. doi: 10.1109/reconfig48160.2019.8994793.
Ko, G.G., Chai, Y., Rutenbar, R.A., Brooks, D., & Wei, G.Y. (2019). FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs. In 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), (p. 334).IEEE. doi: 10.1109/fccm.2019.00075.
Ko, G.G., Chai, Y., Rutenbar, R.A., Brooks, D., & Wei, G.Y. (2019). Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling. In 2019 29th International Conference on Field Programmable Logic and Applications (FPL), (pp. 159-165).IEEE. doi: 10.1109/fpl.2019.00033.
Kim, S., & Rutenbar, R. (2018). Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA. In 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), (p. 218).IEEE. doi: 10.1109/fccm.2018.00052.
Ko, G.G., & Rutenbar, R.A. (2018). Real-Time and Low-Power Streaming Source Separation Using Markov Random Field. In ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 14(2), (pp. 1-22).Association for Computing Machinery (ACM). doi: 10.1145/3183351.
Gao, T., Choi, J., Tsai, S.N., & Rutenbar, R.A. (2017). Toward a pixel-parallel architecture for graph cuts inference on FPGA. In 2017 27th International Conference on Field Programmable Logic and Applications (FPL).IEEE. doi: 10.23919/fpl.2017.8056757.
Ko, G.G., & Rutenbar, R.A. (2017). A case study of machine learning hardware: Real-time source separation using Markov Random Fields via sampling-based inference. In 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), (pp. 2477-2481).IEEE. doi: 10.1109/icassp.2017.7952602.
Choi, J., & Rutenbar, R.A. (2016). Configurable and scalable belief propagation accelerator for computer vision. In 2016 26th International Conference on Field Programmable Logic and Applications (FPL).IEEE. doi: 10.1109/fpl.2016.7577316.
Choi, J., Patil, A.D., Rutenbar, R.A., & Shanbhag, N.R. (2016). Analysis of error resiliency of belief propagation in computer vision. In 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2016-May, (pp. 1060-1064).IEEE. doi: 10.1109/icassp.2016.7471838.
Hurkat, S., Choi, J., Nurvitadhi, E., Martinez, J.F., & Rutenbar, R.A. (2015). Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. In 2015 25th International Conference on Field Programmable Logic and Applications (FPL).IEEE. doi: 10.1109/fpl.2015.7293934.
Guzman-Rivera, A., Kohli, P., Batra, D., & Rutenbar, R.A. (2014). Efficiently enforcing diversity in multi-output structured prediction. In Journal of Machine Learning Research, 33, (pp. 284-292).
Kim, E.P., Choi, J., Shanbhag, N.R., & Rutenbar, R.A. (2014). A robust message passing based stereo matching kernel via system-level error resiliency. In 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), (pp. 8331-8335).IEEE. doi: 10.1109/icassp.2014.6855226.
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Choi, J., & Rutenbar, R.A. (2013). FPGA acceleration of Markov Random Field TRW-S inference for stereo matching. In 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2013, (pp. 139-142).
Choi, J., & Rutenbar, R.A. (2013). Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform. In Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, (pp. 63-71).ACM. doi: 10.1145/2435264.2435278.
Choi, J., Kim, E.P., Rutenbar, R.A., & Shanbhag, N.R. (2013). Error resilient MRF message passing architecture for stereo matching. In SiPS 2013 Proceedings, (pp. 348-353).IEEE. doi: 10.1109/sips.2013.6674531.
Zhang, C., Ko, G.G., Choi, J.W., Tsai, S.N., Kim, M., Rivera, A.G., Rutenbar, R., Smaragdis, P., Park, M.S., Narayanan, V., Xin, H., Mutlu, O., Li, B., Zhao, L., Chen, M., & Iyer, R. (2013). EMERALD: Characterization of emerging applications and algorithms for low-power devices. In 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), (pp. 122-123).IEEE. doi: 10.1109/ispass.2013.6557154.
Zhang, W., Li, X., Saxena, S., Strojwas, A., & Rutenbar, R. (2013). Automatic clustering of wafer spatial signatures. In Proceedings of the 50th Annual Design Automation Conference.ACM. doi: 10.1145/2463209.2488821.
Choi, J., & Rutenbar, R.A. (2012). Hardware implementation of MRF map inference on an FPGA platform. In 22nd International Conference on Field Programmable Logic and Applications (FPL), (pp. 209-216).IEEE. doi: 10.1109/fpl.2012.6339183.
Johnston, J.R., & Rutenbar, R.A. (2012). A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers. In 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, (pp. 77-85).IEEE. doi: 10.1109/asap.2012.25.
Kim, M., Smaragdis, P., Ko, G.G., & Rutenbar, R.A. (2012). Stereophonic spectrogram segmentation using Markov random fields. In 2012 IEEE International Workshop on Machine Learning for Signal Processing.IEEE. doi: 10.1109/mlsp.2012.6349754.
Zhang, W., Balakrishnan, K., Li, X., Boning, D., Acar, E., Liu, F., & Rutenbar, R.A. (2012). Spatial variation decomposition via sparse regression. In 2012 IEEE International Conference on IC Design & Technology.IEEE. doi: 10.1109/icicdt.2012.6232875.
Zhang, W., Balakrishnan, K., Li, X., Boning, D., & Rutenbar, R. (2011). Toward efficient spatial variation decomposition via sparse regression. In 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 162-169).IEEE. doi: 10.1109/iccad.2011.6105321.
Zhang, W., Li, X., & Rutenbar, R.A. (2010). Bayesian virtual probe. In Proceedings of the 47th Design Automation Conference, (pp. 262-267).ACM. doi: 10.1145/1837274.1837342.
Zhang, W., Li, X., Acar, E., Liu, F., & Rutenbar, R. (2010). Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation. In 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 47-54).IEEE. doi: 10.1109/iccad.2010.5654349.
Groeneveld, P., Rutenbar, R.A., Pitera, J., Carlson, E., & Chen, J. (2009). Oil fields, hedge funds, and drugs. In Proceedings of the 46th Annual Design Automation Conference, (pp. 416-417).ACM. doi: 10.1145/1629911.1630021.
Li, X., Rutenbar, R.R., & Blanton, R.D. (2009). Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, (pp. 433-440).
Lin, E.C., & Rutenbar, R.A. (2009). A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer. In Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, (pp. 83-92).ACM. doi: 10.1145/1508128.1508141.
Singhee, A., & Rutenbar, R.A. (2009). SiLVR: Projection Pursuit for Response Surface Modeling. In Lecture Notes in Electrical Engineering, 46 LNEE, (pp. 1-57).Springer Netherlands. doi: 10.1007/978-90-481-3100-6_1.
Yu, K., & Rutenbar, R.A. (2009). Profiling large-vocabulary continuous speech recognition on embedded devices: A hardware resource sensitivity analysis. In Proceedings of the Annual Conference of the International Speech Communication Association, INTERSPEECH, (pp. 1923-1926).
Bourke, P.J., & Rutenbar, R.A. (2008). A low-power hardware search architecture for speech recognition. In Proceedings of the Annual Conference of the International Speech Communication Association, INTERSPEECH, (pp. 2102-2105).
Singhee, A., Fang, C.F., Ma, J.D., & Rutenbar, R.A. (2008). Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools. In IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 27(12), (pp. 2317-2330).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2008.2006142.
Singhee, A., Singhal, S., & Rutenbar, R.A. (2008). Exploiting Correlation Kernels for Ef£cient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing. In 2008 Design, Automation and Test in Europe, (pp. 856-861).IEEE. doi: 10.1109/date.2008.4484781.
Singhee, A., Singhal, S., & Rutenbar, R.A. (2008). Practical, fast Monte Carlo statistical static timing analysis: Why and how. In 2008 IEEE/ACM International Conference on Computer-Aided Design, (pp. 190-195).IEEE. doi: 10.1109/iccad.2008.4681573.
Singhee, A., Wang, J., Calhoun, B.H., & Rutenbar, R.A. (2008). Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. In 21st International Conference on VLSI Design (VLSID 2008), (pp. 131-136).IEEE. doi: 10.1109/vlsi.2008.54.
Jiajing Wang, Singhee, A., Rutenbar, R.A., & Calhoun, B.H. (2007). Statistical modeling for the minimum standby supply voltage of a full SRAM array. In ESSCIRC 2007 - 33rd European Solid-State Circuits Conference, (pp. 400-403).IEEE. doi: 10.1109/esscirc.2007.4430327.
Jones, A.K., Levitan, S., Rutenbar, R.A., & Xie, Y. (2007). Collaborative VLSI-CAD Instruction in the Digital Sandbox. In 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07), (pp. 141-142).IEEE. doi: 10.1109/mse.2007.29.
Lin, E.C., Yu, K., Rutenbar, R.A., & Chen, T. (2007). A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. In Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, (pp. 60-68).ACM. doi: 10.1145/1216919.1216928.
Singhee, A., & Rutenbar, R.A. (2007). Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting. In 2007 44th ACM/IEEE Design Automation Conference, (pp. 256-261).IEEE. doi: 10.1109/dac.2007.375163.
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Singhee, A., & Rutenbar, R.A. (2007). From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis. In 8th International Symposium on Quality Electronic Design (ISQED'07), (pp. 685-692).IEEE. doi: 10.1109/isqed.2007.79.
Xiu, Z., & Rutenbar, R.A. (2007). Mixed-size placement with fixed macrocells using grid-warping. In Proceedings of the 2007 international symposium on Physical design, (pp. 103-110).ACM. doi: 10.1145/1231996.1232019.
Yu, K., & Rutenbar, R.A. (2007). Generating small, accurate acoustic models with a modified bayesian information criterion. In Proceedings of the Annual Conference of the International Speech Communication Association, INTERSPEECH, 2, (pp. 1165-1168).
Borkar, S., Brodersen, R., Chern, J.H., Naviasky, E., Saias, D., & Sodini, C. (2006). Tomorrow's analog. In Proceedings of the 43rd annual conference on Design automation - DAC '06, (pp. 709-710).ACM Press. doi: 10.1145/1146909.1147089.
Frehse, G., Krogh, B.H., & Rutenbar, R.A. (2006). Verifying analog oscillator circuits using forward/backward abstraction refinement. In Proceedings of the Design Automation & Test in Europe Conference, 1.IEEE. doi: 10.1109/date.2006.244113.
Lin, E.C., Kai Yu, Rutenbar, R.A., & Tsuhan Chen. (2006). In silico vox: Towards speech recognition in silicon. In 2006 IEEE Hot Chips 18 Symposium (HCS).IEEE. doi: 10.1109/hotchips.2006.7477867.
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Ma, J.D., & Rutenbar, R.A. (2006). Fast interval-valued statistical modeling of interconnect and effective capacitance. In IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 25(4), (pp. 710-724).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2006.870067.
Rutenbar, R. (2006). Design Automation for Analog: The Next Generation of Tool Challenges. In 2006 IEEE/ACM International Conference on Computer Aided Design, (pp. 458-460).IEEE. doi: 10.1109/iccad.2006.320157.
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Tiwary, S., & Rutenbar, R. (2006). Faster, Parametric Trajectory-based Macromodels Via Localized Linear Reductions. In 2006 IEEE/ACM International Conference on Computer Aided Design, (pp. 876-883).IEEE. doi: 10.1109/iccad.2006.320092.
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Tiwary, S.K., Tiwary, P.K., & Rutenbar, R.A. (2006). Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. In Proceedings of the 43rd annual conference on Design automation - DAC '06, (pp. 31-36).ACM Press. doi: 10.1145/1146909.1146921.
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Ma, J.D., Fang, C.F., Rutenbar, R.A., Xiaolin Xie, & Boning, D.S. (2005). Interval-valued statistical modeling of oxide chemical-mechanical polishing. In ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., 2005, (pp. 141-148).IEEE. doi: 10.1109/iccad.2005.1560054.
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Xiu, Z., Papa, D.A., Chong, P., Albrecht, C., Kuehlmann, A., Rutenbar, R.A., & Markov, I.L. (2005). Early research experience with openaccess gear: An open source development environment for physical design. In Proceedings of the International Symposium on Physical Design, (pp. 94-100).
Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rutenbar, R.A., & Mukherjee, T. (2005). Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. In Design, Automation and Test in Europe, I, (pp. 279-281).IEEE. doi: 10.1109/date.2005.119.
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Tiwary, S.K., Velu, S., Rutenbar, R.A., & Mukherjee, T. (2004). Pareto optimal modeling for efficient PLL optimization. In 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004, 2, (pp. 195-198).
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Zhang, G., Dengi, A., Rohrer, R.A., Rutenbar, R.A., & Carley, L.R. (2004). A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. In Proceedings of the 41st annual Design Automation Conference, (pp. 155-158).ACM. doi: 10.1145/996566.996612.
Fang, C.F., Chen, T., & Rutenbar, R.A. (2003). Floating-point error analysis based on affine arithmetic. In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, 2, (pp. 561-564).
Fang, C.F., Rutenbar, R.A., & Tsuhan Chen. (2003). Fast, accurate static analysis for fixed-point finite-precision effects in DSP designs. In ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486), (pp. 275-282).IEEE. doi: 10.1109/iccad.2003.159701.
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Nam, G.J., Sakallah, K., & Rutenbar, R. (2002). Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2438 LNCS, (pp. 360-369).Springer Berlin Heidelberg. doi: 10.1007/3-540-46117-5_38.
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Dragone, N., Rutenbar, R.A., Carley, L.R., & Zafalon, R. (2001). Low-power technology mapping for mixed-swing logic. In Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, (pp. 291-294).
Gi-Joon Nam, Sakallah, K., & Rutenbar, R. (2001). A Boolean satisfiability-based incremental rerouting approach with application to FPGAs. In Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, (pp. 560-564).IEEE Comput. Soc. doi: 10.1109/date.2001.915079.
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Basaran, B., & Rutenbar, R.A. (1996). O(n) algorithm for transistor stacking with performance constraints. In Proceedings - Design Automation Conference, (pp. 221-226).
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