Pitt | Swanson Engineering
Jones, Alexander Keith
Electrical and Computer Engineering
Jones, Alexander Keith
Director, Computer Engineering Program
Faculty
Associate Professor
Office: 1128 Benedum Hall
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About Dr. Alex Jones

There is an alarming trend of improvement in hardware technology with a significant lag in techniques that utilize the technology. Additionally, there is a trend toward mobile devices with increasing capability and longer battery life. In many cases, these trends are in direct conflict. Current state of the art hardware design methodologies for digital systems require the use of hardware description languages and/or tools that make hardware design for complex systems time-consuming, tedious, and error prone. A popular method to use this die-space is to combine several devices that in the past were contained on separate chips into a single chip called a system-on-a-chip (SoC). This technique buys the industry some time and promotes existing IP reuse; however, the real necessity is a generic solution to digital circuit design for deep and very deep sub-micron technology.

I am interested in solving the design-automation problem to allow new technology to be efficiently used to create new products. It is possible to abstract this problem by targeting traditional high-level programming languages such as C/C++, MATLAB/SIMULINK, and Java for hardware synthesis. Using high-level languages not only provides a much easier interface to the designer, but also allows the opportunity to attack optimization problems at a variety of different levels to produce a more comprehensive solution. In addition to traditional constraints such as optimization of area and performance, these tools must meet new challenges dictated by technology and industry trends such as power optimization.

Toward this end I am interested in developing tools for existing solutions like ASICs and reconfigurable technology such as FPGAs. I am also interested in development of comprehensive solutions for systems that include novel architectures and design tools for high-performance and low-power/mobile applications. 

Ph.D. in Electrical and Computer Engineering, Northwestern University,, 2002

M.Sc. in Computer-aided design and Parallel FPGA design, Northwestern University, 2000

B.Sc. in Physics, The College of William and Mary,, 1998

(2012) Dominion VITA Award.

(2012) ACM SIGDA Service Award.

(2011) Promoted to Senior member of the ACM.

(2010) ACM SIGDA Distinguished Service Award.

(2009) ACM SIGDA Service Award.

(2008) Promoted to Senior member of the IEEE.

(2007) Pitt Innovator Award.

(2005) Featured Paper, Journal of Low Power Electronics, No. 1, Vol. 3.

(2000) Walter P. Murphy Doctoral Fellowship, Northwestern University.

(1998) Received high honors for senior research in Acoustic Music Synthesis as part of my B.Sc. in Physics from the College of William and Mary.

(1998) Graduated cum laude, The College of William and Mary.

(1998) Walter P. Murphy Doctoral Fellowship, Northwestern University.

Li, Y., Jones, A., Zhang, Y., Sun, Z., Chen, Y., and Li, H., 2013, "Staying on Target with X-mode STT-RAM Caches for Fast, Low Power and Reliable Computing," International Symposium on Computer Architecture (ISCA), Manuscript submitted for publication.

Li, Y., Melhem, R., and Jones, A.K., 2012, "PS-TLB: Leveraging Page Classification Information for Fast, Scalable and Efficient Translation for Future CMPs," To appear in ACM Transactions on Architecture and Code Optimization (TACO).

Zhang, Y., Li, Y., Li, H., Chen, Y., and Jones, A.K., 2012, "Staying on Target with X-mode STT-RAM Caches," IEEE Transactions on Circuits and Systems (TCAS) II, Manuscript submitted for publication.

Li, Y., Melhem, R., and Jones, A.K., 2011, "Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors," To appear in IEEE Computer Architecture Letters,, 10.1109/L-CA.2011.35.

Jones, A.K., Liao, L., Collinge, B., Schaefer, L., Landis, A., and Bilec, M., "Green Computing: A Life-Cycle Assessment Perspective," IGCC 2013, Manuscript submitted for publication.

Ihrig, C., and Jones, A.K., In press, "Improving Performance and Reducing Power with Hardware Acceleration: Static Timing Analysis Based transformation of Combinational Logic in an High Level ASIC Synthesis Flow," VDM Publishing.

Li, Y., Zhang, Y., Sun, Z., Li, H., Chen, Y., and Jones, A.K., "Read Performance: The Newest Barrier in Scaled STT-RAM," IEEE Transactions on Circuits and Systems II (TCAS II), Manuscript submitted for publication.

Xu, H., Schaefer, L., Landis, A., Bilec, M., and Jones, A.K., "Ocelot: A Wireless Sensor Network and Computing Engine with Commodity Palmtop Computers," IGCC 2013, Manuscript submitted for publication.

DeBlois, J., Collinge, W., Jones, A.K., Bilec, M.M., and Schaefer, L.A., 2014, "Modeling a Multi-Purpose Public Building with Stochastic Gains and Occupancy Schedules," ASHRAE Winter Meeting, p. 12093, New York, NY.

Li, Y., Zhang, Y., Li, H., Chen, Y., and Jones, A., 2014, "C1C: A Configurable, Compiler-guided STT-RAM L1 Cache," European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC).

Sun, Z., Bi, X., and Jones, A.K., 2014, "Design Exploration of Racetrack Lower-level Caches," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED).

Jones, A.K., Chen, Y., Collinge, W.O., Xu, H., Schaefer, L.A., Landis, A.E., and Bilec, M., 2013, "Considering Fabrication in Sustainable Computing," International Conference on Computer-Aided Design, pp. 206-210, San Jose, CA.

Collinge, W.C., Landis, A.E., Jones, A., Schaefer, L., and Bilec, M., 2013, "A Dynamic Life Cycle Assessment Approach for Whole Building Evaluation," International Journal of Life Cycle Assessment, no.3, pp. 538-552.

Collinge, W.O., Landis, A.E., Jones, A.K., Schaefer, L.A., and Bilec, M.M., 2013, "Indoor Environmental Quality in a Dynamic Life Cycle Assessment Framework for Whole Buildings: Focus on Human Health Chemical Impacts," Building and Environment, pp. 182-190, 10.1016/j.buildenv.2013.01.015.

Li, Y., Zhang, Y., Li, H., Chen, Y., and Jones, A., 2013, "C1C: A Configurable, Compiler-guided STT-RAM L1 Cache," European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) and ACM Transactions on Architecture and Code Optimization (TACO), no.4, p. 52.

Saunders, C., Landis, A.E., Mecca, L.P., Jones, A.K., Schaefer, L.A., and Bilec, M., 2013, "Analyzing the Practice of Life Cycle Assessment: Focus on the Building Sector," Journal of Industrial Ecology.

Saunders, C.L., Landis, A.E., Mecca, L.P., Jones, A.K., Schaefer, L.A., and Bilec, M.M., 2013, "Analyzing the Practice of Life Cycle Assessment: Focus on the Building Sector," Journal of Industrial Ecology, no.5, pp. 777-778, 10.1111/jiec.12028.

Thiel, C., Campion, N., Landis, A.E., Jones, A.K., Schaefer, L.A., and Bilec, M.M., 2013, "A Materials Life Cycle Assessment of a Net-Zero Energy Building," Energies, pp. 1125-1141, 10.3390/en6021125.

Abousamra, A., Jones, A.K., and Melhem, R., 2012, "Co-Design of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors," IEEE Transactions of Parallel and Distributed Computing, no.6, pp. 1038-1046, 10.1109/TPDS.2011.238.

Abousamra, A., Melhem, R., and Jones, A.K., 2012, "Deja Vu Switching for Multiplane NoCs," ACM/IEEE international Symposium on Networks-on-Chip (NOCS), pp. 11-18.

Collinge, W.O., Landis, A.E., Jones, A.K., Schaefer, L.A., and Bilec, M., 2012, "Integrating Indoor Environmental Quality Metrics in a Dynamic Life Cycle Assessment Framework For Buildings," IEEE International Symposium on Sustainable Systems and Technology, Boston, Massachusetts.

Li, Y., Abousamra, A., Melhem, R., and Jones, A.K., 2012, "Compiler-assisted Data Distribution and Network Configuration for Chip Multiprocessors," IEEE Transactions of Parallel and Distributed Computing, no.11, pp. 2058-2066, 10.1109/TPDS.2011.279.

Li, Y., and Jones, A.K., 2012, "Cross-Layer Techniques for Optimizing Systems Utilizing Memories with Asymmetric Access Characteristics," Proceedings of the International Symposium on VLSI (ISVLSI).

Li, Y., Chen, Y., and Jones, A.K., 2012, "A Software Approach for Combating Asymmetries of Non-Volatile Memories," International Symposium on Low Power Electronics and Design (ISLPED), pp. 191-196.

Li, Y., Chen, Y., and Jones, A.K., 2012, "Combating Write Penalties Using Software Dispatch for On-chip MRAM Integration," IEEE Embedded System Letters (ESL), no.4, pp. 82-85.

Li, Y., Melhem, R., and Jones, A.K., 2012, "Practically Private: Enabling High Performance CMPs Through Compiler-assisted Data Classification," Proceedings of the Parallel Architecture and Compilation Techniques (PACT) Conference, pp. 231-240.

Saunders, C.L., Landis, A.E., Jones, A.K., Schaefer, L.A., and Bilec, M., 2012, "Utilizing Measured Energy Usage to Analyze Design Phase Energy Models," 2012 IEEE International Symposium on Sustainable Systems and Technology, Boston, Massachuesetts.

Zhang, Y., Wang, X., Li, Y., Jones, A.K., and Chen, Y., 2012, "Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs," Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1313-1318.

Jones, A.K., and Levitan, S.P., 2011, "Industrially Inspired Just-in-Time (JIT) Teaching," 2011 International Conference on Microelectronic Systems Education, pp. 1-4, San Diego, CA.

Abousamra, A., Jones, A.K., and Melhem, R., 2011, "NoC-Aware Cache Design for Multithreaded Execution on Tiled Chip Multiprocessors," Proc. of High Performance and Embedded Architectures and Compilers (HiPEAC), pp. 197-205.

Abousamra, A., Jones, A.K., and Melhem, R., 2011, "Two-hop free-space based optical interconnects for Chip Multiprocessors," Proc. of NOCS, pp. 89-96.

Collinge, W.O., Liao, L., Xu, H., Saunders, C.L., Bilec, M.M., Landis, A.E., Jones, A.K., and Schaefer, L.A., 2011, "Enabling Dynamic Life Cycle Assessment of Buildings with Wireless Sensor Networks," in Proc. of IEEE International Symposium on Sustainable Systems and Technology (ISSST), pp. 1-6.

Li, Y., Chen, Y., and Jones, A.K., 2011, "Magnetic RAM Integration for CMPs using Hardware-Based Software-Optimized Dispatching," Workshop on Emerging Supercomputing Technologies.

Xu, H., Umez-Eronini, I., Mao, Z.H., and Jones, A.K., 2011, "Towards improving renewable resource utilization with plug-in electric vehicles," 2011 IEEE PES Innovative Smart Grid Technologies (ISGT) Conference, 6 pages, Anaheim, CA, USA.

Abousamra, A., Jones, A.K., and Melhem, R., 2010, "NoC Aware Cache Design for Chip Multiprocessors," ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT).

Ihrig, C., Melhem, R., and Jones, A.K., 2010, "Automated Modeling and Emulation of Interconnect Designs for Many-Core Chip Multiprocessors," Design Automation Conference (DAC).

Li, Y., Abousamra, A., Melhem, R., and Jones, A.K., 2010, "Compiler-assisted Data Distribution for Chip Multiprocessors," ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 501-512.

Li, Y., Melhem, R., and Jones, A.K., 2010, "Compiler-based Data Classification for Hybrid Caching," Proceedings of the ASPLOS Workshop on the Interaction between Compilers and Computer Architectures (INTERACT).

O'Conner, R., Bassi, H., Grainger, B., Taylor, E., Reed, G., Jones, A.K., and Mao, Z., 2010, "Integrated Multisource Generation and Control for Increasing Renewable Generation Utilization," IEEE Annual Power Meeting.

O'Connor, R., Reed, G., Mao, Z.H., and Jones, A.K., 2010, "Improving renewable resource utilization through integrated generation management," 2010 IEEE PES General Meeting, 6 pages, Minneapolis, MN, USA.

O'Connor, R., Reed, G.F., Mao, Z., and Jones, A.K., 2010, "Improving Renewable Resource Utilization through Integrated Generation Management," IEEE PES General Meeting, Minneapolis, Minnesota.

Reed, G.F., Grainger, B.M., Bassi, H., Taylor, E., Mao, Z.H., and Jones, A.K., 2010, "Analysis of high capacity power electronic technologies for integration of green energy management," IEEE PES Transmission and Distribution Conference and Exposition, 10 pages, New Orleans, La, USA.

Wang, H., Reed, G.F., and Jones, A.K., 2010, "Analysis of Recovery Current and Core Structure of DC Power Supply in Electronic Current Transformer," IEEE International Symposium on Industrial Electronics, ISIE 2010, Bari, Italy.

Wang, H., Reed, G.F., and Jones, A.K., 2010, "Review: DC Power Supply of High Voltage Active Electronic Current Transformer," IEEE International Symposium on Industrial Electronics, ISIE 2010, Bari, Italy.

Wang, H., Xu, H., and Jones, A.K., 2010, "Crucial Issues in Logistic Planning for Electric Vehicle Battery Application and Service," International Symposium on Traffic Information and Logistic Engineering (ISTILE).

Jones, A.K., Kerbyson, D.J., Rajamony, R., and Weems, C., 2009, "Guest Editor's Note: Large-Scale Parallel Processing," Parallel Processing Letters, no.4, pp. 487-490.

Abousamra, A., Melhem, R., and Jones, A.K., 2009, "Winning with Pinning in NoC," IEEE Hot Interconnects (HOTI).

Dontharaju, S., Tung, S., Cain, J.T., Mats, L., Mickle, M.H., and Jones, A.K., 2009, "A Design Automation and Power Estimation Flow for RFID Systems," ACM Transactions on Design Automation for Electronic Systems (TODAES), no.1, pp. 1-31, 10.1145/1455229.1455236.

Ihrig, C.J., Dhanablan, G.J., and Jones, A.K., 2009, "A Low-power CMOS Thyristor Based Delay Element With Programmability Extensions," Proc. of GLSVLSI, pp. 297-302.

Mehta, G., Stander, J., Baz, M., Hunsaker, B., and Jones, A.K., 2009, "Interconnect Customization for a Hardware Fabric," ACM Transactions on Design Automation for Electronic Systems (TODAES), no.1, pp. 1-32, 10.1145/1455229.11455240.

Zhang, Y., and Jones, A.K., 2009, "Non-Uniform "Fat-Meshes" For Chip Multiprocessors," Parallel Processing Letters, no.4, pp. 595-617.

Zhang, Y., and Jones, A.K., 2009, "Non-Uniform Fat-Meshes for Chip Multiprocessors," Proc. of the IPDPS Workshop of Large Scale Parallel Processing (LSPP), pp. 1-8.

Jones, A.K., and Walker, R.A., 2008, "Introduction to the Special Issue on Demonstrable Software Systems and Hardware Platforms II," ACM Transactions on Design Automation for Electronics Systems (TODAES), no.3, 10.1145/1367045.1367047.

Jones, A.K., Dontharaju, S., Tung, S., Mats, L., Hawrylak, P., Hoare, R.R., Cain, J.T., and Mickle, M.H., 2008, "Radio Frequency Identification Prototyping," ACM Transactions on Design Automation for Electronic Systems (TODAES), no.2, pp. 1-21, 10.1145/1344418.1344425.

Jones, A.K., Kerbyson, D.J., Rajamony, R., and Weems, C., 2008, "Guest Editor's Note: Large-Scale Parallel Processing," Parallel Processing Letters, no.4, pp. 449-451.

Jones, A.K., Shao, S., Zhang, Y., and Melhem, R., 2008, "Symbolic Expression Analysis for Compiled Communication," Parallel Processing Letters, no.4, pp. 567-587.

Jones, A.K., Tung, S., Dontharaju, S., Dhanabalan, G.J., Hawrylak, P.J., Mats, L., Mickle, M.H., and Cain, J.T., 2008, "Minimum Energy/Power Considerations," in RFID Handbook: Applications, Technology, Security, and Privacy., S. Ahson, and M. Ilyas, eds., pp. 199-230.

Dontharaju, S., Tung, S., Hoare, R.R., Mickle, M.H., Cain, J.T., and Jones, A.K., 2008, "Design Automation for RFID Tags and Systems," in RFID Handbook: Applications, Technology, Security, and Privacy, S. Ahson, and M. Ilyas, eds., pp. 35-64.

Hoare, R., Ding, Z., and Jones, A.K., 2008, "A Near-optimal Two-stage Hardware Scheduler for Large Cardinality Crossbar Switches," Journal of Parallel and Distributed Computing (JPDC), no.11, pp. 1437-1451.

Ihrig, C., Baz, M., Stander, J., Hoare, R.R., Norman, B.A., Hunsaker, B., Prokopyev, O., and Jones, A.K., 2008, "Greedy Algorithms for Mapping onto a Coarse-grained Reconfigurable Fabric head," in Advances in Greedy Algorithms, W. Bednorz, ed., In-Tech, pp. 193-222.

Mehta, G., Ihrig, C., and Jones, A.K., 2008, "Reducing Energy by Exploring Heterogeneity in a Coarse-grain Fabric," Reconfigurable Architecture Workshop (RAW), 104.1 - 104.8.

Mickle, M.H., Cain, J.T., and Jones, A.K., 2008, "Intellectual Property and Ubiquitous RFID," no.1, pp. 59-67.

Shao, S., Zhang, Y., Jones, A.K., and Melhem, R., 2008, "Symbolic Expression Analysis for Compiled Communication," IEEE Workshop on Large Scale Parallel Processing (LSPP), 286.1 - 286.8.

Tung, S., and Jones, A.K., 2008, "Physical Layer Design Automation for RFID Systems," Reconfigurable Architecture Workshop (RAW), 117.1 - 117.8.

Tung, S., Dontharaju, S., Mats, L., Hawrylak, P.J., Mickle, M.H., Cain, J.T., and Jones, A.K., 2008, "Layers of Security for Active RFID Tags," in RFID Handbook: Applications, Technology, Security, and Privacy, S. Ahson, and M. Ilyas, eds., pp. 603-630.

Yu, Y., Hoare, R.R., and Jones, A.K., 2008, "A CAM-based Intrusion Detection System for Single-packet Attack Detection," Reconfigurable Architecture Workshop (RAW), 119.1 - 119.8.

Jones, A.K., Dontharaju, S.R., Mats, L., Cain, J.T., and Mickle, M.H., 2007, "Exploring RFID Prototyping in the Virtual Laboratory," MSE Conference, pp. 137-138.

Jones, A.K., Hoare, R., Dontharaju, S., Tung, S., Sprang, R., Fazekas, J., Cain, J.T., and Mickle, M.H., 2007, "An Automated, FPGA-based Reconfigurable, Low-Power RFID Tag," Journal of Microprocessors and Microsystems, no.2, pp. 116-134.

Jones, A.K., Hoare, R.R., Onge, J.S., Lucas, J., Shao, S., and Melhem, R., 2007, "Linking Compilation and Visualization for Massively Parallel Programs," IPDPS/APDCM Workshop, 228.1 - 228.8.

Dontharaju, S., Tung, S., Jones, A.K., Mats, L., Panuski, J., Cain, J.T., and Mickle, M.H., 2007, "The Unwinding of a Protocol," IEEE Applications and Practice, no.1, pp. 4-9.

Ihrig, C.J., Stander, J., and Jones, A.K., 2007, "Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions," IPDPS/APDCM Workshop, 227.1 - 227.8.

Mehta, G., Stander, J., Baz, M., Hunsaker, B., and Jones, A.K., 2007, "Interconnect Customization for a Coarse-grained Reconfigurable Fabric," IPDPS Reconfigurable Architecture Workshop (RAW), 165.1 - 165.8.

Jones, A.K., Dontharaju, S., Tung, S., Hawrylak, P., Mats, L., Hoare, R., Cain, J.T., and Mickle, M.H., 2006, "Passive Active Radio Frequency Identification Tags (PART)," International Journal of Radio Frequency Identification Technology and Applications (IJRFITA), no.1, pp. 52-73.

Jones, A.K., Hoare, R., Dontharaju, S., Tung, S., Sprang, R., Fazekas, J., Cain, J.T., and Mickle, M.H., 2006, "An Automated, FPGA-based Reconfigurable, Low-Power RFID Tag," Proc. of IEEE/ACM Design Automation Conference (DAC), pp. 131-136.

Jones, A.K., Hoare, R., Dontharaju, S.R., Tung, S., Sprang, R., Fazekas, J., Cain, J.T., and Mickle, M.H., 2006, "A Field Programmable RFID Tag and Associated Design Flow," Proc. of the IEEE Symposium on Field Programmable and Custom Computing Machines (FCCM), pp. 165-174.

Jones, A.K., Hoare, R., Kusic, D., Fazekas, J., Mehta, G., and Foster, J., 2006, "A VLIW Processor with Hardware Functions: Increasing Performance While Reducing Power," IEEE Transactions on Circuits and Systems II, no.11, pp. 1250-1254.

Jones, A.K., Hoare, R., Kusic, D., Mehta, G., Fazekas, J., and Foster, J., 2006, "Reducing Power while Increasing Performance with SuperCISC," ACM Transactions on Embedded Computing Systems (TECS), no.3, pp. 658-686.

2006, "Entropy Based Evaluation of Communication Predictability in Parallel Applications," IEICE Transactions on Information & Systems, no.2, pp. 469-478.

Ding, Z., Hoare, R., Jones, A.K., and Melhem, R., 2006, "Level-wise Scheduling Algorithm for Fat Tree Interconnection Networks," Proc. of Supercomputing (SC), 165.1 - 165.9.

Hawrylak, P.J., Mats, L., Cain, J.T., Jones, A.K., Tung, S., and Mickle, M.H., 2006, "Ultra Low-power Computing Systems for Wireless Devices," International Review on Computers and Software (IRECOS), no.1, pp. 1-10.

Hoare, R., Jones, A.K., Kusic, D., Fazekas, J., Foster, J., Tung, S., and McCloud, M., 2006, "Rapid VLIW Processor Customization For Signal Processing Applications Using Combinational Hardware Functions," EURASIP Journal on Applied Signal Processing (JASP), pp. 1-23, 46473.

Hoare, R., Ding, Z., and Jones, A.K., 2006, "A Near-optimal Real-time Hardware Scheduler for Large Cardinality Crossbar Switches," Proc. of Supercomputing (SC), 164.1 - 164.12.

Lucas, J., Hoare, R., Kourtev, I., and Jones, A.K., 2006, "Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)," Proc. of the IEEE Symposium on Field Programmable and Custom Computing Machines (FCCM), pp. 299-300.

Lucas, J.M., Hoare, R., Kourtev, I.S., and Jones, A.K., 2006, "Technology Mapping for Field Programmable Fate Arrays using Content-Addressable Memory (CAM)," Journal of Microprocessors and Microsystems, no.7, pp. 445-456.

Mehta, G., Hoare, R., Stander, J., and Jones, A.K., 2006, "Design Space Exploration for Low-Power Reconfigurable Fabrics," Proc. of IEEE/ACM Reconfigurable Architectures Workshop (RAW).

Mehta, G., Hoare, R.R., Stander, J., Lucas, J., Hunsaker, B., and Jones, A.K., 2006, "A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture," Journal of Low Power Electronics (JOLPE), no.2, pp. 148-164.

Schuster, J., Gupta, K., Hoare, R., and Jones, A.K., 2006, "Speech Silicon: An FPGA Architecture for Real Time, Hidden Markov Model Based Speech Recognition," EURASIP Journal on Embedded Systems (JES), pp. 1-19, 48085.

Shao, S., Jones, A.K., and Melhem, R., 2006, "A Compiler-based Communication Analysis Approach for Multiprocessor Systems," Proc. of IEEE/ACM International Parallel and Distributed Processing Symposium (IPDPS).

Yu, Y., Hoare, R., Jones, A.K., and Sprang, R., 2006, "A Hybrid Encoding Scheme that Enables Single-cycle Range Matching in Content Addressable Memory," Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 791-794.

Jones, A.K., Hoare, R., Kusic, D., Fazekas, J., and Foster, J., 2005, "An FPGA-based VLIW Processor with Custom Hardware Execution," ACM International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 107-117.

Barker, K.J., Benner, A., Hoare, R., Hoisie, A., Jones, A.K., Kerbyson, D.J., Li, D., Melhem, R., Rajamony, R., Schenfeld, E., Shao, S., Stunkel, C., and Walker, P.A., 2005, "On the Feasibility of Optical Circuit Switching for High Performance Computing Systems," IEEE/ACM Supercomputing Conference (SC), pp. 16-1 - 16-22.

Hoare, R., Jones, A.K., Kusic, D., Fazekas, J., Mehta, G., and Foster, J., 2005, "A VLIW Processor with Hardware Functions: Increasing Performance While Reducing Power," Proc. of HPEC, pp. 5-6.

Hoare, R., Ding, Z., Tung, S., Melhem, R., and Jones, A.K., 2005, "A Framework for the Design, Synthesis and Cycle-Accurate Simulation of Multiprocessor Networks," Journal of Parallel and Distributed Computing, no.10, pp. 1237-1252.

Kusic, D., Hoare, R., Jones, A.K., Fazekas, J., and Foster, J., 2005, "Extracting Speedup from C-code with Poor Instruction-level Parallelism," Workshop of Massively Parallel Processing (WMPP), pp. 264-9 - 264-18.

Lucas, J., Hoare, R., Kourtev, I., and Jones, A.K., 2005, "LURU2: Optimizing Technology Mapping for FPGAs Using CAMs," IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 293-294.

Melhem, R., Hoare, R., Jones, A.K., Ding, Z., Tung, S., Li, D., Shao, S., and Zheng, J., 2005, "Enabling Predictive Multiplexed Switching in Multiprocessor Networks," International Parallel & Distributed Processing Symposium, pp. 100-1 - 100-10.

Tang, X., Jiang, T., Jones, A.K., and Banerjee, P., 2005, "Behavioral Synthesis of Data Dominated Circuits for Minimal Energy Implementation," IEEE International Conference on VLSI Design,, pp. 267-273, Taj Bengal, Kolkata, India.

Tang, X., Jiang, T., Jones, A.K., and Banerjee, P., 2005, "Behavioral Synthesis with power Estimation and Optimization for Unscheduled Data-Dominated Circuits," Journal of Low Power Electronics, no.3, pp. 259-272.

Jones, A.K., Hoare, R., Kourtev, I., Fazekas, J., Kusic, D., Foster, J., Boddie, S., and Muaydh, A., 2004, "A 64-way VLIW/SIMD FPGA Processing Architecture and Design Flow," International Conference on Electronics, Circuits, and Systems (ICECS), pp. 499-502, Tel Aviv, Israel.

Jones, A.K., Tang, X., and Banerjee, P., 2004, "Compile-time Simulation for Low-Power Optimization using SystemC," Modelling and Simulation Conference, pp. 78-83, Marina Del Ray, CA.

Brady, B., Jones, A.K., and Kourtev, I., 2004, "Efficient CAD Development for Emerging Technologies using Objective-C and Cocoa," International Conference on Electronics, Circuits, and Systems (ICECS), pp. 369-372, Tel Aviv, Israel.

Brady, B., Jones, A.K., and Kourtev, I., 2004, "Rapid CAD Prototyping for Nanotechnology using Objective-C and Cocoa," University of Pittsburgh ECE Department Technical Report: TR-ECE-2004-04- 001.

Lucas, J., Hoare, R., Kourtev, I., and Jones, A.K., 2004, "LURU: Global Scope FPGA Technology Mapping with Content-Addressable Memories," International Conference on Electronics, Circuits, and Systems (ICECS), pp. 599-602, Tel Aviv, Israel.

Mukherjee, R., Jones, A.K., and Banerjee, P., 2004, "Handling Data Streams while Compiling C Programs onto Hardware," International Symposium on VLSI (ISVLSI), pp. 271-272, Lafayette, Louisiana.

Tang, X., Jiang, T., Jones, A.K., and Banerjee, P., 2004, "Behavioral Synthesis with Power Estimation and Optimization for Unscheduled Data-Dominated Circuits," Center for Parallel and Distributed Computing Technical Report: CPDC-TR-2004-03-001.

Jones, A.K., and Banerjee, P., 2003, "An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs," ACM International Symposium on Field-Programmable Gate Arrays (FPGA), p. 244, Monterey, California.

Jones, A.K., and Banerjee, P., 2003, "An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs," IEEE Symposium on Field- Programmable Custom Computing Machines (FCCM), pp. 284-285, Napa, CA.

Jiang, T., Tang, X., Jones, A.K., and Banerjee, P., 2003, "Optimizing Power While Exploiting Fine Grain Parallelism on FPGAs," IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS), pp. 357-362.

Mukherjee, R., Jones, A.K., and Banerjee, P., 2003, "System Level Synthesis of Multiple IP Blocks in the Behavioral Synthesis Tool," International Conference on Parallel and Distributed Computing and Systems (PDCS), pp. 363-368.

Tang, X., Jiang, T., Jones, A.K., and Banerjee, P., 2003, "Compiler Optimizations in the PACT HDL Behavioral Synthesis Tool for ASICs and FPGAs," IEEE International SoC Conference (SoC), pp. 189-192.

Jones, A.K., and Banerjee, P., 2002, "An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions," Center for Parallel and Distributed Computing Technical Report: CPDC-TR-2002-04-02.

Jones, A.K., Bagchi, D., Pal, S., Banerjee, P., and Choudhary, A., 2002, "A Compiler with Power and Performance Optimizations," in Power Aware Computing, R. Graybill, and R. Melhem, eds., Kluwer Academic Publishers.

Jones, A.K., Bagchi, D., Pal, S., Tang, X., Choudhary, A., and Banerjee, P., 2002, "PACT HDL: A C Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations," Center for Parallel and Distributed Computing Technical Report: CPDC-TR-2002-03-01.

Jones, A.K., Bagchi, D., Pal, S., Tang, X., Choudhary, A., and Banerjee, P., 2002, "PACT HDL: A C Compiler with Power and Performance Optimizations," International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 188-197, Grenoble, France.

Jones, A.K., Nayak, A., and Banerjee, P., 2001, "Parallel Implementation of Matrix and Signal Processing Libraries on FPGAs," International Conference on Parallel and Distributed Computing and Systems (PDCS), pp. 370-377, Anaheim, CA.

Bagchi, D., Pal, S., Jones, A.K., Choudhary, A., and Banerjee, P., 2001, "Pipelining Memory Accesses on FPGAs for Image Processing Algorithms," Center for Parallel and Distributed Computing Technical Report: CPDC-TR-2001-12-002.

Banerjee, P., Shenoy, N., Choudhary, A., Hauck, S., Bachmann, C., Chang, M., Haldar, M., Joisha, P., Jones, A.K., Kanhare, A., Nayak, A., Periyacheri, S., and Walkden, M., 2000, "MATCH: A MATLAB Compilation Environment for Configurable Computing Systems," International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 39-48, Napa, CA.

Banerjee, P., Shenoy, N., Choudhary, A., Hauck, S., Bachmann, C., Chang, M., Haldar, M., Joisha, P., Jones, A.K., Kanhare, A., Nayak, A., Periyacheri, S., and Walkden, M., 1999, "MATCH: A MATLAB Compiler for Configurable Computing Systems," Center for Parallel and Distributed Computing Technical Report: CPDC-TR-9908-013.

Periyacheri, S., Jones, A.K., Nayak, A., Zaretsky, D., Banerjee, P., Shenoy, N., and Choudhary, A., 1999, "Library Functions in Reconfigurable Hardware for Matrix and Signal Processing Operations in MATLAB," International Conference on Parallel and Distributed Computing and Systems (PDCS 1999), Cambridge, MA.

Jones, A.K., and Levitan, S.P., "Industrially Inspired Just-in-time (JIT) teaching," 2011 International Conference on Microelectronic Systems Education, pp. 1-4, San Diego, CA.

Jones, A.K., Levitan, S., Rutenbar, R.A., and Yuan, X., "Collaborative VLSI- CAD Instruction in the Digital Sandbox," Microsystems Educators Workshop (MSE'07), pp. 141-142, San Diego, CA.

Jones, A.K., Levitan, S.P., Rutenbar, R.A., and Xie, Y., "Collaborative VLSI-CAD Instruction in the Digital Sandbox," Microsystems Educators Workshop (MSE'07), pp. 141-142, San Diego, CA.

Abousamra, A., Jones, A.K., and Melhem, R., "Proactive Circuit Allocation in Multiplane NoCs, Proceedings of the Design Automation Conference (DAC)."

Collinge, W.O., Bilec, M.M., Landis, A.E., Jones, A.K., and Schaefer, L.A., "Scenario Modeling for Dynamic Life Cycle Assessment of Commercial and Institutional Building," Proceedings of LCA XI, Chicago, Illinois.

Collinge, W.O., Deblois, J., Sweriduk, M., Landis, A.E., Jones, A.K., Schaefer, L.A., and Bilec, M.M., "Measuring Whole-Building Performance with Dynamic Life-Cycle Assessment: A Case Study of a Green University Building," Proceedings from International Symposium on LCA and Construction, Nantes, France.

Hoare, R., Jones, A.K., Kusic, D., Fazekas, J., Mehta, G., and Foster, J., "A VLIW Processor with Hardware Functions: Increasing Performance While Reducing Power," Proc. of the Workshop on High Performance Embedded Computing (HPEC'05).

Mao, M., Li, H., Jones, A.K., and Chen, Y., "Coordinating Prefetching and STT-RAM-based Last-level Cache Management for Multicore Systems," GLSVLSI 2013.

Mehta, G., Hoare, R., Stander, J., and Jones, A.K., "A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture," Proc. of the IEEE Symposium on Field Programmable and Custom Computing Machines (FCCM), pp. 309-310.

Shao, S., Jones, A.K., and Melhem, R., "Compiler Techniques for Efficient Communications in Circuit Switched Networks for Multiprocessor Systems," IEEE Transactions for Parallel and Distributed Systems (TPDS), no.3, pp. 331-345.

Collinge, W.O., Landis, A.E., Jones, A.K., Schaefer, L.A., and Bilec, M., 2013, "Synergistic Scenarios for Indoor Health and Productivity in Whole-Building Life Cycle Assessment," International Symposium on Sustainable Systems and Technology, Cincinnati, Ohio.

Mao, M., Li, H., Jones, A., Xue, J., and Chen, Y., 2013, "Dynamic Prefetch Aggressiveness Tuning for STT-RAM-based Last-level Cache," 4th Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW4).

Olinzock, M., Landis, A.E., Schaefer, L.A., Jones, A.K., and Bilec, M., 2013, "Results of a National Survey Regarding Whole-Building Life Cycle Assessments Among the Architecture, Engineering, and Construction Community," International Symposium on Sustainable Systems and Technology, Cincinnati, Ohio.

Saunders, C.L., Landis, A.E., Schaefer, L.A., Jones, A.K., and Bilec, M., 2013, "Understanding Energy Models Results in the Context of a Building's Lifetime: Focus on a High Performance Building," International Symposium on Sustainable Systems and Technology, Cincinnati, Ohio.

Collinge, W.O., Deblois, J., Sweriduk, M., Landis, A.E., Jones, A.K., Schaefer, L.A., and Bilec, M., 2012, "Measuring Whole-Building Performance with Dynamic Life-Cycle Assessment: A Case Study of a Green University Building," International Symposium on LCA and Construction, Nantes, France.

Collinge, W.O., Landis, A.E., Jones, A.K., Schaefer, L.A., and Bilec, M., 2012, "Integrating Indoor Environmental Quality Metrics in a Dynamic Life Cycle Assessment Framework For Buildings," 2012 IEEE International Symposium on Sustainable Systems and Technology, Boston, Massachuesetts.

Saunders, C.L., Landis, A.E., Jones, A.K., Schaefer, L.A., and Bilec, M., 2012, "Utilizing Measured Energy Usage to Analyze Design Phase Energy Models," 2012 IEEE International Symposium on Sustainable Systems and Technology, Boston, Massachuesetts.

Collinge, W.C., Saunders, C., Bilec, M., Landis, A.E., and Jones, A., 2011, "Framework and Data Acquisition for an Automated, Dynamic Building Life Cycle Assessment.," Poster Engineering Sustainability 2011, Pittsburgh, Pennsylvania.

Collinge, W.O., Bilec, M., Landis, A.E., Jones, A.K., and Schaefer, L.A., 2011, "Scenario Modeling for Dynamic Life Cycle Assessment of Commercial and Institutional Building," Presentation, American Center for Life Cycle Assessment, Proceedings of LCA XI, Chicago, Illinois.

Collinge, W.O., Liao, L., Xu, H., Saunders, C.L., Bilec, M., Landis, A.E., Jones, A.K., and Schaefer, L.A., 2011, "Enabling Dynamic Life Cycle Assessment of Buildings with Wireless Sensor Networks," Presentation, 2011 IEEE International Symposium on Sustainable Systems and Technology, Chicago, Illinois.

Li, Y., Chen, Y., and Jones, A., 2011, "Magnetic RAM Integration for CMPs using Hardware-Based Software-Optimized Dispatching," Workshop on Emerging Supercomputing Technologies (WEST, in conjunction with International Conference on Supercomputing).

2007, "Low-energy Reconfigurable Computing," Virginia Tech.

2004, "Hardware Devices and Electronic Design Automation," Westinghouse, Inc..

2004, "The Data Forest Supercomputer," Northrup Grumman, Corp..

2003, "PACT HDL: A C Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations," Illinois Institute of Technology.

2003, "PACT HDL: A Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations," University of Tennessee.