Pitt | Swanson Engineering
Yang, Jun
Electrical and Computer Engineering
Yang, Jun
Director, ECE Graduate Program
Faculty
Professor
Office: 1111 Benedum Hall
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Ph.D. in Computer Science, University of Arizona, 2002

M.S. in Computer Science, University of Pittsburgh, 1999

M.A. in Applied Mathematics, Worcester Polytechnic Institute, 1997

B.S. in Computer Science, Nanjing University, 1995

Embedded systems

Hardware security

Memory systems

Processor microarchitecture

(2009) Best Paper Nominee, The 15th International Symposium on High-Performance Computer Architecture.

(2008) NSF Faculty Early Career Development Award (CAREER).

(2007) Best Paper, ISLPED 2013; ICCD, processor architecture track.

(2003) Regent's Faculty Fellowship / Faculty Development Award.

Jiang, L., Du, Y., Zhao, B., Zhang, Y., Childers, B., and Yang, J., In press, "Hardware Asissited Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory," ACM Transactions on Architecture and Code Optimization.

Zhou, P., Zhao, B., Zhang, Y., and Yang, J., In press, "Throughput Enhancement for Phase Change Memories," IEEE Transactions on Computers.

Guo, J., Yang, J., Zhang, Y., and Chen, Y., 2013, "Low Cost Power Failure Protection for MLC NAND Flash Storage Systems with PRAM/DRAM Hybrid Buffer," Design, Automation and Test in Europe (DATE), pp. 859-864.

Zhang, X., Jiang, L., Zhang, Y., Zhang, C., and Yang, J., 2013, "WoM-SET: Lowering Write Power of Proactive-SET based PCM Write Strategy Using WoM Code," The International Symposium on Low Power Electronics and Design, pp. 217-222.

Zhao, B., Zhang, Y., and Yang, J., 2013, "A Speculative Arbiter Design to Enable High-Frequency Many-VC Router in NoCs," the 7th International Symposium on Networks-on-Chip, pp. 1-8.

Zhou, P., Zhang, Y., and Yang, J., 2013, "The Design of Sustainable Wireless Sensor Network Node using Solar Energy and Phase Change Memory," Design, Automation and Test in Europe (DATE), pp. 869-872.

Jiang, L., Zhang, Y., and Yang, J., 2012, "ER: Elastic RESET for Low Power and Long Endurance MLC Based Phase Change Memory," International Symposium on Low Power Electronics and Design (ISLPED), pp. 39-44.

Jiang, L., Zhang, Y., Childers, B., and Yang, J., 2012, "FPB: Fine-grained Power Budgeting to Im-prove Write Throughput of Multi-level Cell Phase Change Memory," the 45th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 1-12.

Jiang, L., Zhao, B., Zhang, Y., Yang, J., and Childers, B., 2012, "Improving Write Operations in MLC Phase Change Memory," the 18th International Symposium on High-Performance Computer Architecture (HPCA), pp. 201-210.

Jiang, L., Zhao, B., Zhang, Y., and Yang, J., 2012, "Constructing Large and Fast Multi-Level Cell STT-MRAM Based Cache for Embedded Processors," the 49th Design Automation Conference (DAC), pp. 907-912.

Xu, Y., Yang, J., and Melhem, R., 2012, "Channel Borrowing: An Energy-Efficient Nanophotonic Crossbar Architecture with Light-Weight Arbitration," International Conference on Supercomputing (ICS), pp. 133-142.

Xu, Y., Yang, J., and Melhem, R., 2012, "Tolerating Process Variations in Nanophotonic On-chip Net-works," the 39th International Symposium on Computer Architecture (ISCA), pp. 142-152.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., and Li, H., 2012, "Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices," Design, Automation and Test in Europe (DATE), pp. 1451-1454.

Zhao, B., Du, Y., Yang, J., and Zhang, Y., 2012, "Process Variation Aware Non-Uniform Cache Management in 3D Die Stacked Multicore Processor," IEEE Transactions on Computers.

Jiang, L., Du, Y., Zhang, Y., Childers, B., and Yang, J., 2011, "LLS: Cooperative Integration of Wear-Leveling and Salvaging for PCM Main Memory," IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), pp. 221-232.

Jiang, L., Zhang, Y., and Yang, J., 2011, "Enhancing Phase Change Memory Lifetime Through Fine-Grained Current Regulation and Voltage Upscaling," The International Symposium on Low Power Electronics and Design (ISLEPD), pp. 127-132.

Li, L., Zhang, Y., and Yang, J., 2011, "Proactive Recovery for BTI in High-K SRAM Cells," Design, Automation and Test in Europe (DATE), pp. 992-997.

Xu, Y., Du, Y., Zhang, Y., and Yang, J., 2011, "A Composite and Scalable Cache Coherence Protocol for Large Scale CMPs," the 25th International conference on Supercomputing (ICS), pp. 285-294.

Yang, J., Gao, L., Zhang, Y., Chrobak, M., and Lee, H., 2010, "A Low-Cost Memory Remapping Scheme for Address Bus Protection," Journal of Parallel and Distributed Computing Elsevier, vol.70, no.5, pp. 443-457.

Lee, B., Zhou, P., Ipek, E., Mutlu, O., Yang, J., Zhang, Y., Zhao, B., and Burger, D., 2010, "Phase Change Technology and the Future of Main Memory," IEEE Micro, vol.30, no.1, pp. 131-143.

Li, L., Zhang, Y., Yang, J., and Zhao, J., 2010, "Proactive NBTI Mitigation for Busy Functional Units in Out-of-Order Microprocessors," Design, Automation and Test in Europe (DATE), pp. 411-416.

Xia, L., Zhu, Y., Yang, J., Ye, J., and Gu, Z., 2010, "Implementing a Thermal-aware Scheduler in Linux Kernel on a Multi-core Processor," The Computer Journal (Oxford University Press), vol.53, no.7, pp. 895-903.

Xu, Y., Zhao, B., Zhang, Y., and Yang, J., 2010, "Simple Virtual Channel Allocation for High Throughput and High Frequency On-chip Routers," the 16th International Symposium on High-Performance Computer Architecture (HPCA), 11 pages.

Zhang, Y., Yang, J., Li, W., Wang, L., and Jin, L., 2010, "An Authentication Scheme for Locating Compromised Sensor Nodes in WSNs," Journal of Network and Computer Applications, vol.33, no.1, pp. 50-62.

Zhang, Y., Yang, J., Vu, H., and Wu, Y., 2010, "The Design and Evaluation of Interleaved Au-thentication for Filtering False Reports in Multipath Routing WSNs," Wireless Networks, The Journal of Mobile Communication, Computation and Information, Springer Netherlands, vol.16, no.1, pp. 125-140.

Zhou, P., Du, Y., Zhang, Y., and Yang, J., 2010, "Fine-grained QoS Scheduling for PCM-based Main Memory Systems," the 24th IEEE International Symposium on Parallel and Distributed Processing (IPDPS), 12 pages.

Zhou, X., Yang, J., Chrobak, M., and Zhang, Y., 2010, "Performance-aware Thermal Manage-ment via Task Scheduling," ACM Transactions on Architecture and Code Optimization, vol.7, no.1.

Zhou, X., Yang, J., Xu, Y., Zhang, Y., and Zhao, J., 2010, "Thermal-aware Task Scheduling for 3D Multi-core Processors," IEEE Transactions on Parallel and Distributed Systems, vol.21, no.1, pp. 60-71.

Li, W., Zhang, Y., Yang, J., and Zheng, J., 2009, "Towards Update-Conscious Compilation for Energy-Efficient Code Dissemination in WSNs," ACM Transactions on Architecture and Code Optimization, vol.6, no.4.

Suresh, D., Agrawal, B., Yang, J., and Najjar, W., 2009, "Energy-Efficient Encoding Techniques for Off-Chip Data Buses," ACM Transactions on Embedded Computing Systems, vol.8, no.2;9.

Suresh, D., Agrawal, B., Yang, J., and Najjar, W., 2009, "Tunable and Energy Efficient Bus En-coding Techniques," IEEE Transactions on Computers, vol.58, no.8, pp. 1049-1062.

Xu, Y., Du, Y., Zhao, B., Zhou, X., Zhang, Y., and Yang, J., 2009, "A Low-Radix and Low-Diameter 3D Interconnection Network Design," the 15th International Sympsium on High-Performance Computer Architecture (HPCA), pp. 30-41.

Zhang, Y., Yang, J., and Gao, L., 2009, "Supporting Flexible Streaming Media Protection through Privacy-aware Secure Processors," Journal of Computers and Electrical Engineering, Elsevier, Special Issue on Circuits and Systems for Real-Time Security and Copyright Protection of Multimedia, vol.35, no.2, pp. 286-299.

Zhao, B., Du, Y., Zhang, Y., and Yang, J., 2009, "Variation-Tolerant Non-Uniform 3D Cache Man-agement in Die Stacked Multicore Processor," the 42nd IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 222-231.

Zhou, P., Zhao, B., Yang, J., and Zhang, Y., 2009, "A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology," the 36th International Symposium on Computer Architecture (ISCA), pp. 14-23.

Zhou, P., Zhao, B., Yang, J., and Zhang, Y., 2009, "Energy Reduction for STT-RAM Using Early Write Termination," IEEE/ACM 2009 International Conference on Computer-Aided Design (ICCAD), pp. 264-268.

Zhou, P., Zhao, B., Xu, Y., Du, Y., Zhang, Y., Yang, J., and Zhao, L., 2009, "Frequent Value Com-pression in Packet-based NoC Architectures," the 14th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 13-18.

Yang, J., Zhou, X., Chrobak, M., Zhang, Y., and Jin, L., 2008, "Dynamic Thermal Man-agement through Task Scheduling," IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 191-201.

Zhou, X., Xu, Y., Du, Y., Zhang, Y., and Yang, J., 2008, "Thermal Management for 3D Processors via Task Scheduling," the 37th International Conference on Parallel Processing (ICPP), pp. 115-122.

Li, W., Zhang, Y., Yang, J., and Zheng, J., 2007, "UCC: Update-conscious Compilation for En-ergy-efficiency in Wireless Sensor Networks," ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), pp. 383-393.

Luo, Y., Yu, J., Yang, J., and Bhuyan, L., 2007, "Conserving Network Processor Power Consump-tion by Exploiting Traffic Variability," ACM Transactions on Architecture and Code Optimization, vol.4, no.1;4, 26 pages.

Wu, W., Yang, J., Tan, S., and Lu, S., 2007, "Improving the Reliability of On-Chip Caches Under Process Variations," IEEE International Conference on Computer Design (ICCD), pp. 325-332.

Wu, W., Jin, L., Yang, J., Liu, P., and Tan, S., 2007, "Efficient Power Modeling and Soft-ware Thermal Sensing for Runtime Temperature Monitoring," ACM Transactions on Design Automation of Electronic Systems, Special Issue on Demonstrable Software Systems and Hardware Plat-forms, vol.12, no.3;26, 29 pages.

Yu, J., Yao, J., Bhuyan, L., and Yang, J., 2007, "Program Mapping for Network Processors by Recursive Bipartitioning and Refining," the 44th IEEE/ACM Design Automation Conference (DAC), pp. 805-810.

Gao, L., Yang, J., Chrobak, M., Zhang, Y., Nguyen, S., and Lee, H., 2006, "A Low-cost Memory Remapping Scheme for Address Bus Protection," the 15th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 74-83.

Jin, L., Wu, W., Yang, J., Zhang, C., and Zhang, Y., 2006, "Reduce Register File Leak-age through Cell Discharging," IEEE International Conference on Computer Design (ICCD).

Li, W., Zhang, Y., and Yang, J., 2006, "Dynamic Authentication-key Reassignment for Reliable Report Delivery," IEEE 3rd International Conference on Mobile Ad-hoc and Sensor Systems, pp. 467-476.

Liu, P., Li, H., Jin, L., Wu, W., Tan, S., and Yang, J., 2006, "Fast Thermal Simulation for Runtime Temperature Tracking and Management," IEEE Transactions on Computer-Aided Desing of Integrated Circuits and Systems, vol.25, no.12, pp. 2882-2894.

Shi, W., Fryman, J., Lee, H., Zhang, Y., and Yang, J., 2006, "InfoShield: A Security Architecture for Protecting Information Usage in Memory," the 12th IEEE International Sympsoium on High-Performance Computer Architecture (HPCA), pp. 225-234.

Wu, W., Jin, L., Yang, J., Liu, P., and Tan, S., 2006, ""Efficient Method for Functional Unit Power Estimation in Modern Microprocessors," the 43th IEEE/ACM Design Automation Conference (DAC), pp. 554-557.

Zhang, Y., Yang, J., and Vu, H., 2006, "Interleaved Authentication for Filtering False Reports in Multipath Routing Based Sensor Networks," IEEE International Parallel and Distributed Processing Symposium (IPDPS).

Zhang, Y., Yang, J., Jin, L., and Li, W., 2006, "Locating Compromised Sensor Nodes through Incremental Hashing Authentication," IEEE International Conference on Distributed Computing in Sensor Systems (DCOSS), pp. 321-337.

Yang, J., Gao, L., and Zhang, Y., 2005, "Improving Memory Encryption Performance in Secure Processors," IEEE Transactions on Computers, vol.54, no.5, pp. 630-340.

Yang, J., Yu, J., and Zhang, Y., 2005, "A Low Energy Cache Design for Multimedia Applications Exploiting Set Access Locality," Journal of systems Architecture: the EUROMICRO Journal, vol.51, no.10-11, pp. 653-664.

Jin, L., Wu, W., Yang, J., Zhang, C., and Zhang, Y., 2005, "Dynamic Co-allocation of Resources for Level One Caches," the 2nd International Conference on Embedded Software and Systems, pp. 373-385.

Li, H., Liu, P., Qi, Z., Jin, L., Wu, W., and Tan, S., 2005, "Efficient Thermal Simulation for Run-Time Temperature Tracking and Management," IEEE International Conference on Computer Design (ICCD), pp. 130-133.

Lin, Y., Zhang, Y., Li, Q., and Yang, J., 2005, "Supporting Efficient Query Processing on Compressed XML Files," the 20th ACM annual Symposium on Applied computing (SAC), pp. 660-665.

Liu, P., Qi, Z., Li, H., Jin, L., Wu, W., and Tan, S., 2005, "Fast Thermal Simulation for Architecture Level Dynamic Thermal Management," IEEE International Conference on Computer-Aided Design (ICCAD), pp. 638-643.

Luo, Y., Yu, J., Yang, J., and Bhuyan, L., 2005, "Low Power Network Processor Design Using Clock Gating," the 42nd IEEE/ACM Design Automation Conference (DAC), pp. 712-715.

Suresh, D., Agrawal, B., Najjar, W., and Yang, J., 2005, "Tunable Bus Encoder for off-Chip Data Buses," IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 319-322.

Suresh, D., Agrawal, B., Najjar, W., and Yang, J., 2005, "VALVE: Variable Length Value Encod-ing for Off-Chip Data Busses," IEEE International Conference on Computer Design (ICCD), pp. 631-633.

Yu, J., Yang, J., chen, S., Luo, Y., and Bhuyan, L., 2005, "Enhancing Network Processor Simu-lation Speed with Statistical Input Sampling," 2005 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC), LNCS, pp. 68-83.

Yu, J., Wu, W., Chen, X., Hsieh, H., Yang, J., and Balarin, F., 2005, "Assertion-Based Automatic De-sign Exploration of DVS in Network Processor Architectures," Design, Automation and Test in Europe (DATE), pp. 92-97.

Zhang, C., Vahid, F., Yang, J., and Najjar, W., 2005, "A Way-Halting Cache for Low-Energy High-Performance Systems," ACM Transactions on Architecture and Code Optimization, vol.2, no.1, pp. 34-54.

Zhang, Y., and Yang, J., 2005, "Reducing I-cache Energy of Multimedia Applications through Low Cost Tag Comparison Elimination," Journal of Embedded Computing, vol.1, no.4, pp. 461-470.

Zhang, Y., Gao, L., Yang, J., Zhang, X., and Gupta, R., 2005, "SENSS: Security Enhance-ment to Symmetric Shared Memory Multiprocessors," the 11th IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp. 352-362.

Yang, J., Gupta, R., and Zhang, C., 2004, "Frequent Value Encoding for Low Power Data Bus-es," ACM Transactions on Design Automation of Electronic Systems, vol.9, no.3, pp. 354-384.

Zhang, C., Yang, J., and Vahid, F., 2004, "Low Static Power High Performance Frequent Value Data Caches," Design, Automation & Text in Europe (DATE), pp. 214-219.

Zhang, C., Vahid, F., Yang, J., and Najjar, W., 2004, "A Way-Halting Cache for Low-Energy High Performance Systems," IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 126-131.

Yang, J., Yu, J., and Zhang, Y., 2003, "Lightweight Set Buffer: Low Power Data Cache for Multime-dia Applications," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 270-273.

Yang, J., Zhang, Y., and Gao, L., 2003, "Fast Secure Processors for Inhibiting Software Privacy and Tampering," ACM/IEEE 36th International Symposium on Microarchitecture (MICRO), pp. 351-360.

Suresh, D., Yang, J., Zhang, C., Agrawal, B., and Najjar, W., 2003, "Reducing Transition Activity on Data Bas," the 10th Annual International Conference on High Performance Computing (HiPC), pp. 44-54.

Suresh, D., Agrawal, B., Yang, J., Najjar, W., and Bhuyan, L., 2003, "Power Efficient Encod-ing Techniques for Off-chip Data Buses," ACM International Conference on Comilers, Architecture and Synthesis for Embedded Systems (CASES), pp. 267-275.

Zhang, Y., and Yang, J., 2003, "Low Cost Instruction Cache Design for Tag Comparison Elimination," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 266-269.

Zhang, Y., and Yang, J., 2003, "Procedural Level Address Offset Assignment of DSP Applications with Loops," IEEE International Conference on Parallel Processing (ICPP), pp. 21-28.

Yang, J., and Gupta, R., 2002, "Energy Efficient Frequent Value Data Cache Design," ACM/IEEE the 35th International Symposium on Microarchitecture (MICRO), pp. 197-207.

Yang, J., and Gupta, R., 2002, "Frequent Value Locality and Its Applications," ACM Transactions on Embedded Computing Systems (inaugural issue), vol.1, no.1, pp. 79-105.

Yang, J., and Gupta, R., 2001, "Energy-Efficient Load and Store Reuse," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 72-75.

Yang, J., and Gupta, R., 2001, "FV Encoding for Low-Power Data I/O," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 84-87.

Yang, J., and Gupta, R., 2000, "Load Redundancy Removal through Instruction Reuse," IEEE International Conference on Parallel Processing (ICPP), pp. 61-68.

Yang, J., Zhang, Y., and Gupta, R., 2000, "Frequent Value Compression in Data Caches," ACM/IEEE the 33rd International Symposium on Microarchitecture (MICRO), pp. 258-265.

Tang, D., and Yang, J., 2000, "Free Moving Boundary Model and Boundary Iteration Method for Unsteady Viscous Flow in Stenotic Elastic Tubes," SIAM Journal on Scientific Computing, vol.21, no.4, pp. 1370-1386.

Zhang, Y., Yang, J., and Gupta, R., 2000, "Frequent Value Locality and Value-Centric Data Cache Design," ACM 9th International Conference on Architecture Support for Programming Languages and Operating Systems (ASPLOS), pp. 150-159.

Tang, D., Yang, J., Yang, C., and Ku, D.N., 1999, "A Nonlinear Axisymmetric Model with Flu-id-Wall Interactions for Viscous Flows in Stenotic Elastic Tubes," Journal of Biomechanical Engineering, vol.121, pp. 494-501.

Yang, J., 2013, "WoM-SET: Lowering Write Power of Proactive-SET based PCM Write Strategy Using WoM Code," International Symposium on Low Power Electronics and Design, Beijing, China.

Yang, J., 2009, "Frequent Value Compression in Packet-based NoC Architectures," 14th Asia and South Pacific Design Automation Conference, Yokohama, Japan.

Yang, J., 2008, "A Low-Radix and Low-Diameter 3D Interconnection Network Design," Computer Architecture Lab at Carnegie Mellon (CALCM), ECE Department, Carnegie Mellon University.

Yang, J., 2008, "A Low-Radix and Low-Diameter 3D Interconnection Network Design," Computer Science and Technology Department, Nanjing University, Nanjing, China.

Yang, J., 2008, "Dynamic Thermal Management through Task Scheduling," 2008 IEEE Interna-tional Symposium on Performance Analysis of Systems and Software, Austin, TX.

Yang, J., 2007, "Dynamic Thermal Monitoring and Management for High-Performance Microprocessor," Intel Research Lab, Pittsburgh, PA.

Yang, J., 2006, "Dynamic Power and Thermal Monitoring and Managements for High-Performance Micropro-cessors," Department Graduate Seminar.

Yang, J., 2006, "Dynamic Power and Thermal Monitoring and Managements for High-Performance Micropro-cessors," Intel Asia-Pacific Research Development, Ltd. Shanghai, China.

Yang, J., 2006, "Dynamic Power and Thermal Monitoring and Managements for High-Performance Micropro-cessors," School of Microelectronics, Shanghai Jiaotong University, Shanghai, China.

Yang, J., 2006, "Dynamic Power and Thermal Monitoring for High-Performance Microprocessors," Computer Science Department, University of Pittsburgh.

Yang, J., 2006, "Dynamic Power and Thermal Monitoring for High-Performance Microprocessors," Department of Computer Science and Engineering, Pennsylvania State University.

Yang, J., 2006, "Load Redundancy Removal through Instruction Reuse," ECE Department Undergraduate Seminar.

Yang, J., 2006, "Low Power and Thermal Management for High-Performance Microprocessor Designs," IEEE Chapter, Undergraduate Seminar ECE Department.

Yang, J., 2006, "Towards an Energy and Thermally Efficient High-Performance Microprocessor Design," ECE Department Undergraduate Seminar.

Yang, J., 2002, "Frequent Value Phenomenon and its Applications," Computer Science Department, Rutgers, the State University of New Jersey.

Yang, J., 2002, "Frequent Value Phenomenon and its Applications," Department of Computer and Information Sciences, University of Delaware.

Yang, J., 2002, "Frequent Value Phenomenon and its Applications," Department of Computer Sci-ence and Engineering, University of California Riverside.

Yang, J., 2002, "Frequent Value Phenomenon and its Applications," Department of Computer Science and Engineering, University of Connecticut.

Yang, J., 2002, "Frequent Value Phenomenon and its Applications," Department of Computer Science and Engineering, University of North Texas.

Yang, J., 2002, "Frequent Value Phenomenon and its Applications," Department of Computer Science and Engineering, University of Texas Arlington.

Yang, J., 2002, "Frequent Value Phenomenon and its Applications," Department of Computer Science, State University of New York Binghamton.

Yang, J., 2001, "Energy-Efficient Load and Store Reuse," ACM/IEEE International Symposium on Low Power Electronics and Design, Huntington Beach, CA.

Yang, J., 2001, "FV Encoding for Low-Power Data I/O," ACM/IEEE International Symposium on Low Power Electronics and Design, Huntington Beach, CA.

Yang, J., 2000, "Frequent Value Compression in Data Caches," ACM/IEEE 33rd International Sym-posium on Microarchitecture, Monterey, CA.

Yang, J., 2000, "Load Redundancy Removal through Instruction Reuse," International Conference on parallel Processing, Toronto, Canada.

Publication Role 
IEEE Computer Architecture Letter Associate Editor