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PhD in Computer Engineering. Thesis: "Reliability and test of high-speed integrated circuits", University of Texas, 2003

MS in Computer Engineering. Thesis: "Recent advances in partitioned ordered binary decision diagrams", University of Texas, 2000

BTech in Electrical Engineering, Indian Institute of Technology, 1998

(2012) Graphene research covered in Nature article on graphene electronics.

(2011) Finalist, Phi Beta Kappa Teaching Prize, Rice University.

(2011) Top accessed article, IEEE Electron Device Letters.

(2011) Top accessed article, IEEE Trans. Computer-aided Design.

(2011) Top accessed article, IEEE Trans. Nanotechnology.

(2010) ACS Nano article covered by MIT Technology Review, Physics World, Nanowerk, EE Times, and other technology portals.

(2010) Best paper award nomination, International Conference on Computer-aided Design.

(2010) Distinguished Faculty Associate, McMurtry College, Rice University.

(2010) Finalist, Phi Beta Kappa Teaching Prize, Rice University.

(2009) Associate Editor, IEEE Transactions on VLSI Systems.

(2009) Top 10 downloaded papers, IEEE Transactions on Computer-aided Design.

(2008) National Science Foundation CAREER Award.

(2007) A. Richard Newton Graduate Scholarship.

(2006) Technical Leadership Award, ACM Special Interest Group on Design Automation (ACM/SIGDA).

Hunter, N.A., and **Mohanram, K.**, 2014, "Single-ended codes to improve the endurance of phase change memory," Design, Automation and Test in Europe, Manuscript submitted for publication.

Li, J., and **Mohanram, K.**, 2014, "Virtual multi-port phase change memory," Intl. Symposium on High Performance Computer Architecture, Manuscript submitted for publication.

Li, J., and **Mohanram, K.**, 2014, "Write-once-encoded phase change memory for high performance computing applications," Intl. Symposium on High Performance Computer Architecture, Manuscript submitted for publication.

Choudhury, M.R., and **Mohanram, K.**, In press, "Low cost concurrent error masking using approximate logic circuits," IEEE Trans. Computer-aided Design.

Choudhury, M.R., Chandra, V., Aitken, R., and **Mohanram, K.**, In press, "Time-borrowing circuit designs and hardware prototyping for timing error resilience," IEEE Trans. Computers.

Choudhury, M.R., and **Mohanram, K.**, "Performance optimization using lookahead logic circuits," IEEE Trans. Computer-aided Design, Manuscript submitted for publication.

Garg, A., Cara, D., Degueurce, G., Ibberson, M., Dorier, J., Xenarios, I., and **Mohanram, K.**, "Efficient computation of minimal perturbation sets in gene regulatory networks," Frontiers in Physiology, Manuscript submitted for publication.

Li, J., Zhao, Y., Dgien, N., Hunter, A., and **Mohanram, K.**, "Two-port phase change memory architecture for network processing applications," IEEE Trans. VLSI Systems, Manuscript submitted for publication.

Yang, X., and **Mohanram, K.**, "Unequal-error-protection codes for error-tolerant applications," IEEE Trans. Computer-aided Design, Manuscript submitted for publication.

**Mohanram, K.**, and Iyer, S., 2013, "Memsecure: Enabling orders of magnitude reduction in embedded memory certification
and trust effort," Government Microcircuit Applications and Critical Technology Conference.

**Mohanram, K.**, Wartell, M., and Iyer, S., 2013, "Mempack: An order of magnitude reduction in the cost, risk, and time
for memory compiler certification," Design, Automation and Test in Europe, pp. 1490-1493.

Li, J., Zhao, Y., Dgien, D., Hunter, N.A., and **Mohanram, K.**, 2013, "Dual-port PCM architecture for network processing," Non-Volatile Memories Workshop.

Zhao, Y., Li, J., and **Mohanram, K.**, 2013, "Multi-port FinFET SRAM design," Great Lakes Symposium on VLSI, pp. 293-298.

Du, K., Varman, P., and **Mohanram, K.**, 2012, "High performance reliable variable latency carry select addition," Design, Automation and Test in Europe, pp. 1257-1262.

Yang, X., Liu, G., Tostami, M., and Balandin, A.A., 2012, "Graphene circuits for analog, mixed-signal, and RF electronics," Intl. Sympsoium Nanoscale Architectures, pp. 1-6.

Choudhury, M.R., Yoon, J., Guo, J., and **Mohanram, K.**, 2011, "Graphene nanoribbon FETs: Technology exploration for performance and reliability," IEEE Electron Device Letters, vol.32, no.3, pp. 231-233.

Du, K., Varman, P., and **Mohanram, K.**, 2011, "Static window addition: A new paradigm for the design of variable latency adders," Intl. Conference Computer Design, pp. 455-456.

Garg, A., **Mohanram, K.**, di Cara, A., De Micheli, G., and Xenarios, I., 2011, "Implicit methods for qualitative modeling
of gene regulatory networks," in Gene Regulatory Networks: Methods and Protocols, Springer Publishers, pp. 397-443.

Jamaa, B.H., **Mohanram, K.**, and Micheli, D.G., 2011, "An efficient gate library for ambipolar CNTFET logic," IEEE Trans. Computer-aided Design, vol.30, no.2, pp. 242-255.

Rostami, M., and **Mohanram, K.**, 2011, "Dual-Vth independent-gate FinFETs for low power logic circuits," IEEE Trans. Computer-aided Design, vol.30, no.3, pp. 337-349.

Yang, X., and **Mohanram, K.**, 2011, "Modeling and performance investigation of the double-gate carbon nanotube transistor," IEEE Electron Device Letters, vol.32, no.3, pp. 231-233.

Yang, X., and **Mohanram, K.**, 2011, "Robust 6T Si tunneling transistor SRAM," Design, Automation and Test in Europe, pp. 740-745.

Yang, X., and **Mohanram, K.**, 2011, "Unequal-error-protection codes in SRAMs for mobile multimedia applications," Intl. Conference Computer-aided Design, pp. 21-27.

Yang, X., Liu, G., Rostami, M., Balandin, A.A., and **Mohanram, K.**, 2011, "Graphene ambipolar multiplier phase detector," IEEE Electron Device Letters, vol.32, no.10, pp. 1328-1330.

Zukoski, A., Choudhury, M.R., and **Mohanram, K.**, 2011, "Reliability-driven don't care assignment for logic synthesis," Design, Automation and Test in Europe, pp. 1560-1565.

Zukoski, A., Yang, X., and **Mohanram, K.**, 2011, "Universal logic modules based on double-gate carbon nanotube transistors," Design Automation Conference, pp. 884-889.

**Mohanram, K.**, and Yang, X., 2010, "Graphene nanoribbon transistors and circuits," in Nanoelectronic
Circuit Design, Springer Publishers, pp. 349-376.

Choudhury, M.R., and **Mohanram, K.**, 2010, "Bi-decomposition of large Boolean functions using blocking edge graphs," Intl. Conference Computer-aided Design.

Choudhury, M.R., Chandra, V., **Mohanram, K.**, and Aitken, R., 2010, "Analytical model for TDDB-based performance
degradation in combinational logic," Design, Automation and Test in Europe, pp. 423-428.

Choudhury, M.R., Chandra, V., **Mohanram, K.**, and Aitken, R., 2010, "TIMBER: Time borrowing and error relaying for online timing error resilience," Design, Automation and Test in Europe, pp. 1554-1559.

Choudhury, M.R., Rostami, M., and **Mohanram, K.**, 2010, "Dominant critical gate identification for power and yield optimization in logic circuits," Great Lakes Symposium on VLSI, pp. 173-178.

Jamaa, B.H., **Mohanram, K.**, and De Micheli, G., 2010, "Power consumption of logic circuits in ambipolar carbon nanotube technology," Design, Automation and Test in Europe, pp. 303-306.

Rostami, M., and **Mohanram, K.**, 2010, "Novel dual-Vth independent-gate FinFET circuits," Asia and South Pacific Design Automation Conference, pp. 867-872.

Rostami, M., and **Mohanram, K.**, 2010, "Robust inference of biological Bayesian networks," Intl. Workshop on Bio-Design Automation.

Yang, X., Chauhan, J., Guo, J., and **Mohanram, K.**, 2010, "Graphene tunneling FET and its applications in low-power circuit design," Great Lakes Symposium on VLSI, pp. 263-268.

Yang, X., Fiori, G., Iannaccone, G., and **Mohanram, K.**, 2010, "Physics-based semi-analytical model for Schottky-barrier
carbon nanotube and graphene nanoribbon transistors," Great Lakes Symposium on VLSI, pp. 233-238.

Yang, X., Liu, G., Balandin, A.A., and **Mohanram, K.**, 2010, "Triple-mode single-transistor graphene amplifier and its applications," ACS Nano, vol.4, no.10, pp. 5532-5538.

Choudhury, M.R., and **Mohanram, K.**, 2009, "Masking timing errors on speed-paths in logic circuits," Design, Automation and Test in Europe, pp. 87-92.

Choudhury, M.R., and **Mohanram, K.**, 2009, "Reliability analysis of logic circuits," IEEE Trans. Computer-aided Design, vol.28, pp. 392-405.

Choudhury, M.R., Zhou, Q., and **Mohanram, K.**, 2009, "Soft error rate reduction using circuit optimization and transient
filter insertion," Journal of Electronic Testing: Theory and Applications, vol.25, pp. 197-207.

Garg, A., **Mohanram, K.**, Di Cara, A., De Micheli, G., and Xenarios, I., 2009, "Modeling stochasticity and robustness in
gene regulatory networks," Bioinformatics, vol.25, i101-i109.

Garg, A., **Mohanram, K.**, di Cara, A., Xenarios, I., and De Micheli, G., 2009, "Modeling stochasitcity and robustness in gene regulatory networks," Int. Conference on Intelligent Systems for Molecular Biology, i101-i109.

Garg, A., **Mohanram, K.**, di Cara, A., Xenarios, I., and De Micheli, G., 2009, "Timing-driven opimization using lookahead logic circuits," Design Automation Conference, pp. 390-395.

Jamaa, B.H., **Mohanram, K.**, and De Micheli, G., 2009, "Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis," Design, Automation and Test in Europe, pp. 622-627.

Massoud, Y., Kirolos, S., and **Mohanram, K.**, 2009, "Analytical model-based technique for efficient evaluation of noise
robustness considering parameter variations," Analog Integrated Circuits and Signal PRocessing, vol.60, pp. 27-34.

**Mohanram, K.**, 2008, "Error detection and tolerance for scaled electronic technologies," Intl. Sympsoium on Defect and Fault Tolerance in VLSI Systems, pp. 83-83.

**Mohanram, K.**, and Guo, J., 2008, "Graphene nanoribbon FETs: Technology exploration and CAD," Intl. Conference Computer-aided Design, pp. 412-415.

Choudhury, M.R., and **Mohanram, K.**, 2008, "Approximate logic circuits for low overhead, non-intrusive concurrent error detection," Design, Automation and Test in Europe, pp. 903-908.

Choudhury, M.R., Yoon, Y., Guo, J., and **Mohanram, K.**, 2008, "Technology exploration for graphene nanoribbon FETs," Design Automation Conference, pp. 272-277.

Zhao, P., Choudhury, M.R., **Mohanram, K.**, and Guo, J., 2008, "Analytical theory of graphene nanoribbon transistors," Intl. Workshop on Design and Test of Nano Devices, Circuits and Systems, pp. 3-6.

Zhao, P., Choudhury, M.R., **Mohanram, K.**, and Guo, J., 2008, "Computational model of edge effects in grapheme nanoribbon transistors," Nano Research, vol.1, pp. 395-402.

Zhou, Q., Choudhury, M.R., and **Mohanram, K.**, 2008, "Tunable transient filters for soft error rate reduction in combinational circuits," European Test Symposium, pp. 179-184.

Choudhury, M.R., and **Mohanram, K.**, 2007, "Accurate and scalable reliability analysis of logic circuits," Design, Automation and Test in Europe, pp. 1454-1459.

Choudhury, M.R., Ringgenberg, K., Rixner, S., and **Mohanram, K.**, 2007, "Single-ended coding techniques for off-chip interconnects to commodity memory," Design, Automation and Test in Europe, pp. 1072-1077.

Kirolos, S., Mondal, M., **Mohanram, K.**, and Massoud, Y., 2007, "A model-based technique for efficient evaluation of noise robustness," Intl. Midwest Symposium on Circuits and Systems, pp. 714-717.

Mondal, M., **Mohanram, K.**, and Massoud, Y., 2007, "Parameter-variation-aware analysis for noise robustness," Intl. Symposium on Quality Electronic Design, pp. 655-659.

Sun, K., Zhou, Q., **Mohanram, K.**, and Sorensen, D.C., 2007, "Parallel domain decomposition for simulation of large-scale power grids," Intl. Conference Computer-aided Design, pp. 54-59.

Choudhury, M.R., Zhou, Q., and **Mohanram, K.**, 2006, "Design Optimization for single-event upset robustness using simultaneous dual-Vdd and sizing techniques," Intl. Conference Computer-aided Design.

Cox, A.L., **Mohanram, K.**, and Rixner, S., 2006, "Dependable =/ Unaffordable," Workshop on Architectural and System Support for Improving Software Dependability, pp. 58-62.

Zhou, Q., and **Mohanram, K.**, 2006, "Elmore model for energy estimation in RC trees," Design Automation Conference, pp. 965-970.

Zhou, Q., and **Mohanram, K.**, 2006, "Gate sizing to radiation harden combinational logic," IEEE Trans. Computer-aided Design, vol.25, pp. 155-166.

Zhou, Q., Choudhury, M.R., and **Mohanram, K.**, 2006, "Design optimization for robustness to single event upsets," VLSI Test Symposium, pp. 202-207.

Zhou, Q., Sun, K., **Mohanram, K.**, and Sorensen, D.C., 2006, "Large power grid analysis using domain decomposition," Design, Automation and Test in Europe, pp. 27-32.

**Mohanram, K.**, 2005, "Closed-form simulation and robustness models for SEU-tolerant design," VLSI Test Symposium, pp. 327-333.

**Mohanram, K.**, 2005, "Simulation of transients caused by single-event upsets in combinational logic," Intl. Test Conference, pp. 973-981.

**Mohanram, K.**, and Rixner, S., 2005, "Context-independent codes for off-chip interconnects," Lecture notes in Computer Science, B. Falsafi, and T.N. Vijaykumar, eds., pp. 107-119.

Zhou, Q., **Mohanram, K.**, and Antoulas, A.C., 2005, "Structure preserving reduction of frequency-dependent interconnect," Design Automation Conference, pp. 939-942.

**Mohanram, K.**, and Touba, N.A., 2004, "Lowering power consumption in concurrent checkers via input ordering," IEEE Trans. VLSI Systems, vol.12, pp. 1234-1243.

Zhou, Q., and **Mohanram, K.**, 2004, "Analysis of delay caused by bridging faults in RLC interconnects," Intl. Test Conference, pp. 1044-1052.

Zhou, Q., and **Mohanram, K.**, 2004, "Cost-effective radiation hardening technique for logic circuits," Intl. Conference Computer-aided Design, pp. 100-106.

Zhou, Q., and **Mohanram, K.**, 2004, "Transistor sizing for radiation hardening," Intl. Reliability Physics Symposium, pp. 310-315.

**Mohanram, K.**, and Touba, N.A., 2003, "Cost-effective approach for reducing soft error failure rate in logic circuits," Intl. Test Conference, pp. 893-901.

**Mohanram, K.**, and Touba, N.A., 2003, "Eliminating non-determinism during test of high-speed source synchronous
differential buses," VLSI Test Symposium, pp. 121-127.

**Mohanram, K.**, and Touba, N.A., 2003, "Partial error masking to reduce soft error failure rate in logic circuits," Intl. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 433-440.

**Mohanram, K.**, Sogomonyan, E.S., Gossel, M., and Touba, N.A., 2003, "Synthesis of low-cost parity-based partially
self-checking circuits," Intl. On-line Testing Symposium, pp. 35-40.

**Mohanram, K.**, and Touba, N.A., 2002, "Input ordering in concurrent checkers to reduce power consumption," Intl. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 87-95.

**Mohanram, K.**, Krishna, C.V., and Touba, N.A., 2002, "A methodology for automated insertion of concurrent error
detection hardware in synthesizable Verilog RTL," Intl. Symposium on Circuits and Systems, pp. 577-580.

Jain, J., **Mohanram, K.**, Moundanos, D., Wegener, I., and Lu, Y., 2000, "Analysis of composition complexity and how to
obtain smaller canonical graphs," Design Automation Conference, pp. 681-686.

Jas, A., **Mohanram, K.**, and Touba, N.A., 1999, "An embedded core DFT scheme to obtain highly compressed test sets," Asian Test Symposium, pp. 275-280.

Iyer, S., Chuang, S.T., Nguyen, T., Joshi, S., and Kablanian, A., 2013, "Methods and apparatus for designing," 13/732,372.

Rixner, S., **Mohanram, K.**, and Choudhury, M.R., 2011, "System and method for context-independent codes for off-chip," 7,979,666.