Pitt | Swanson Engineering
Li, Hai
Electrical and Computer Engineering

PhD in Electrical and Computer Engineering, Purdue University, 2004

MS in Microelectronics, Tsinghua University, 2000

BS in Electronic Engineering, Tsinghua University, 1998

3D Integration Technology and Design

Architecture/Circuit/Device Co-optimization for Low-Power

Memory Design and Architecture

Neuromorphic Architecture for Brain-Inspired Computing Systems

(2013) DARPA Young Faculty Award (YFA).

(2013) Best Paper Nomination, International Conference on Computer Aided Desing (ICCAD) for the paper titled "Unleashing the POtential of MLC STT-RAM Caches".

(2013) Best Paper Award, Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI (GLSVLSI) for the paper titled "Coordinating Prefetching and STT-RAM based Last-level Cache Management for Multicore Systems.

(2013) Air Force Visiting Faculty Research Program (VFRP) Fellowship, AFRL/RIB, Rome, NY.

(2012) NSF Career Program.

(2012) WICAT Center and NYU WIRELESS Research Distribution Award.

(2012) Best Paper Nomination, International Conference on Computer Aided Design (ICCAD) for the paper titled "Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches,".

(2011) Air Force Summer Faculty Fellowship Program Award (AF-SFFP), AFRL/RITC, Rome, NY, summer 2011. (Ranking 2 of 300+ applicants) (F49620-02-C-0015).

(2011) Best Paper Nomination, Asia and South Pacific Design Automation Conference (ASP-DAC) for the paper titled "Geometry Variations Analysis of TiO2 Thin Film and Spintronic Memristors".

(2010) Best Paper Nomination, Design, Automation & Test in Europe Conference and Exhibition (DATE) for the paper titled "A Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM),".

(2010) Best Paper Award, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) for the paper titled "Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM".

(2010) Best Paper Nomination, the 11th International Symposium on Quality Electronic Design (ISQED) for the paper titled "Scalability of PCMO-based Resistive Switch Device in DSM Technologies.

(2008) Best Paper Award, the 9th International Symposium on Quality Electronic Design (ISQED) for paper titled "Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)".

(2007) Intel Penryn Project Award for contribution on power reduction methodology, Microprocessor Product Group, Intel Corporation.

(2005) Qualstar Award for 65nm unified design methodology, Qualcomm CDMA Technology, Qualcomm Inc..

Sun, Z., Bi, X., Wu, W., Yoo, S., and Li, H., 2014, "Array Organization and Data Management Exploration in Racetrack Memory," To appear in IEEE Transactions on Computers (TC).

Li, H., In press, "Spintronic Devices: from Memory to Memristor.""Spintronic Devices: from Memory to Memristor."

Chen, Y., Wong, W.F., Li, H., and Cheng, C.K., In press, "Processor Caches built using Multi-Level Spin-Transfer Torque RAM Cells," ACM Journal on Emerging Technologies in Computing Systems (JETC).

Chen, Y.C., Li, H., Zhang, W., and Pino, R., In press, "3-Dimensional High-Density Interleaved Memory for Bipolar RRAM Design," IEEE Transactions on Nanotechnology (TNANO).

Hu, M., Li, H., Chen, Y., Rose, G., Wu, Q., and Linderman, W., In press, "Hardware Realization of Neural Network Using Memristor Crossbar Arrays," IEEE Transactions on Neural Network and Learning System (TNNLS).

Sun, Z., Bi, X., Li, H., Wong, W.F., and Zhu, X., In press, "Multi Retention Level STT-RAM Cache Designs with a Memristor-controlled Refresh Scheme," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems.

Zhang, Y., Bi, X., Chen, Y., and Li, H., In press, "The Optimization of STT-RAM Read/Write and Design Consideration with MTJ Temperature Dependence," in Emerging Metallic Spintronics, X. Wang, ed., CRC Press.

Liu, X., Mao, M., Bi, X., Li, H., and Chen, Y., 2015, "STT-RAM based Register File in GPU Architectures," 19th Asia and South Pacific Design Automation Conference (ASPDAC).

Zhang, C., Sun, G., Zhang, W., Mi, F., Li, H., and Zhao, W., 2015, "Quantitative Modeling of Racetrack Memory, A Tradeoff among Area, Performance, and Power," 19th Asia and South Pacific Design Automation Conference (ASPDAC).

Li, H., 2014, "Memristor Modelings - from Static, Statistical, to Stochastic Methodologies," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Clearwater, FL.

Li, H., Hu, M., Li, C., and Duan, S., 2014, "Memristor Modeling - Static, Statistical, and Stochastic Methodologies," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL.

Li, H., Hu, M., Liu, X., Mao, M., Li, C., and Duan, S., 2014, "Emerging Memristor Technology Enabled Next Generation Cortical Processor," 27th IEEE International SoC Conference (SoCC), Las Vegas, NV.

Li, H., Liu, X., Mao, M., Chen, Y., Wu, Q., and Barnell, M., 2014, "Neuromorphic Hardware Acceleration Enabled by Emerging Technologies," International Symposium on Integrated Circuits (ISIC), Singapore.

Li, H., Sun, Z., Bi, X., Wong, W.F., Zhu, X., and Wu, W., 2014, "STT-RAM Cache Hierarchy Design and Exploration with Emerging Magnetic Devices," in Emerging Memory Technologies - Design, Architecture, and Applicants; ISBN: 978-1-4419-9550-6, Y. Xie, ed., Springer.

Chen, L., Li, C., Huang, T., He, X., Li, H., and Chen, Y., 2014, "STDP Learning Rule Based on Memristor with STDP Property," International Joint Conference on Neural Networks (IJCNN), pp. 1-6.

Chen, Y., Li, H., and Sun, Z., 2014, "Spintronic Memristor as Interface between DNA and Solid State Devices," in Memristors and Memristive Systems. ISBN: 978-1-4614-9067-8, R. Tetzlaff, ed., Springer.

Dong, Z., Duan, S., Hu, X., Wang, L., and Li, H., 2014, "A Novel Memristive Multilayer Feedforward Small-World Neural Network with its Applications in PID Control," Scientific World Journal, no.384828.

Eken, E., Zhang, Y., Wen, W., Joshi, R., Li, H., and Chen, Y., 2014, "A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability," 50th Annual Design Automation Conference (DAC), pp. 1-6.

Eken, E., Zhang, Y., Wen, W., Joshi, R., Li, H., and Chen, Y., 2014, "A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability," IEEE International Magnetics Conference (InterMag), Dresden, Germany.

Hu, M., Li, H., Chen, Y., Wu, Q., Rose, G., and Linderman, W., 2014, "Memristor Crossbar Based Neuromorphic Computing System: A Case Study," IEEE Transactions on Neural Network and Learning System (TNNLS), no.10, pp. 1864-1878.

Hu, M., Wang, Y., Qiu, Q., Chen, Y., and Li, H., 2014, "The Stochastic Modeling of TiO2 Memristor and Its Usage in Neuromorphic System Design," The 19th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 831-836.

Hu, X., Li, H., Chen, Y., and Duan, S., 2014, "An Adjustable Memristor Model and Its Application in Small-world Neural Networks," International Joint Conference on Neural Networks (IJCNN), pp. 7-14.

Li, B., Wang, Y., Chen, Y., Li, H., and Yang, H., 2014, "ICE: Inline Calibration for Memristor Crossbar-based Computing Engine," Design, Automation & Test in Europe Conference & Exhibition (DATE).

Li, Y., Zhang, Y., Li, H., Chen, Y., and Jones, A., 2014, "C1C: A Configurable, Compiler-guided STT-RAM L1 Cache," European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC).

Liang, H., Chen, Y.C., Zhang, W., and Li, H., 2014, "Hierarchical Library-Based Power Estimator for Versatile FPGAs," ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA.

Liu, B., LI, X., Li, H., and Chen, Y., 2014, "Reduction and IR-drop Compensations Techniques for Reliable Neuromorphic Computing," International Conference on Computer Aided Design (ICCAD).

Liu, C., and Li, H., 2014, "A Weighted Sensing Scheme for ReRAM-based Cross-point Memory Array," IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Liu, X., Mao, M., Li, H., Chen, Y., Jiang, H., YAng, J., Wu, Q., and Barnell, M., 2014, "A Heterogeneous Computing System with Memristor-Based Neuromorphic Accelerators," IEEE High Performance Extreme Computing Conference (HPEC).

Mao, F., Chen, Y.C., Zhang, W., and Li, H., 2014, "BMP: A Fast B*-Tree based Modular Placer for FPGAs," ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA.

Mao, M., Wen, W., Zhang, Y., Li, H., and Chen, Y., 2014, "Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory," 50th Annual Design Automation Conference (DAC), pp. 1-6.

Park, E., Li, H., Yoo, S., and Lee, S., 2014, "Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation," Design, Automation & Test in Europe Conference and Exhibition (DATE), pp. 1-4.

Sun, Z., Bi, X., Li, H., Wong, W.F., and Zhu, X., 2014, "STT-RAM Cache Hierarchy with Multi-retention MTJ Designs," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, no.6, pp. 1281-1293.

Sun, Z., Bi, X., and Jones, A.K., 2014, "Design Exploration of Racetrack Lower-level Caches," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED).

Tang, T., Li, B., Wang, Y., Luo, R., and Li, H., 2014, "Energy Efficient Spiking Neural Network Design with RRAM Devices," International Symposium on Integrated Circuits (ISIC), Singapore.

Wang, J., Tim, Y., Wong, W.F., Ong, Z.L., Sun, Z., and Li, H., 2014, "A Coherent Hybrid SRAM and STT-RAM L1 Cache Architecture for Shared Memory Multicores," The 19th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 610-615.

Wang, J., Wong, W.F., and Li, H., 2014, "Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration," 32nd IEEE International Conference on Computer Design (ICCD).

Wu, Q., Liu, B., Chen, Y., Li, H., Chen, Q., and Qiu, Q., 2014, "Bio-Inspired Computing with Resistive Memories - Models, Architectures and Applications," IEEE International Symposium on Circuits and Systems (ISCAS), Australia.

Zhang, Y., Wen, W., Li, H., and Chen, Y., 2014, "The Prospect of STT-RAM Scaling," in Metallic Spintronic Devices. ISBN 978-1-4665-8844-8, X. WAng, ed., CRC Press.

Li, H., 2013, "The Stochastic Characteristics of Memristor Devices and Case Studies in Neuromorphic Hardware De-sign," International Semiconductor Device Research Symposium (ISDRS), Maryland.

Bi, X., Li, H., and Chen, Y., 2013, "STT-RAM Designs Supporting Dual-port Accesses," Design, Automation & Test in Europe Conference and Exhibition (DATE).

Bi, X., Mao, M., Wang, D., and Li, H., 2013, "Unleashing the Potential of MLC STT-RAM Caches," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 429-436.

Chen, X., and Li, H., 2013, "P-Spectrum: A Personalized Smartphone Power Management Technique based on Real-time Battery and User Behavior Monitoring," 50th Design Automation Conference (DAC), Austin, TX.

Chen, Y., Wong, W.F., Li, H., Cheng, C.K., Zhang, Y., and Wen, W., 2013, "On-chip Caches Built on Multi-level Spin-transfer Torque RAM Cells and Its Optimizations," ACM Journal on Emerging Technologies in Computing Systems (JETC), no.2;16, DOI: 10.1145/2463585.2463592.

Chen, Y.C., Zhang, W., and Li, H., 2013, "A Hardware Security Scheme for RRAM-based FPGA," The 23rd International Conference on Field Programmable Logic and Applications (FPL), pp. 1-4.

Guo, J., Sun, G., Xue, J., and Li, H., 2013, "The Detection of Malicious Data Attack on NAND Flash Storage System based on Power Signature," 50th Design Automation Conference (DAC), Austin, TX.

Ji, F., Li, H., Wysocki, B., Thiem, C., and McDonald, N., 2013, "Memristor-based Synapse Design and a Case Study in Reconfigurable Systems," International Joint Conference on Neural Networks (IJCNN).

Li, Y., Zhang, Y., Li, H., Chen, Y., and Jones, A., 2013, "C1C: A Configurable, Compiler-guided STT-RAM L1 Cache," European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) and ACM Transactions on Architecture and Code Optimization (TACO), no.4, p. 52.

Liu, B., Hu, M., Li, H., Chen, Y., and Xue, J., 2013, "Bio-inspired Ultra Lower-power Neuromorphic Computing Engine for Embedded Systems," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Liu, B., Hu, M., Li, H., Huang, T., Mao, Z.H., and Chen, Y., 2013, "Digital-Assisted Noise Eliminating Training For Memristor Crossbar-Based Analog Neuromorphic Computing Engine," Design Automation Conference (DAC).

Liu, B., Hu, M., Li, H., Mao, Z.H., Chen, Y., Huang, T., and Zhang, W., 2013, "Digital-Assisted Noise Eliminating Training For Memristor Crossbar-Based Analog Neuromorphic Computing Engine," 50th Annual Design Automation Conference (DAC).

Sun, Z., Wu, Q., and Li, H., 2013, "Cross-Layer Racetrack Memory Design For Ultra High Density And Low Power Consumption," Design Automation Conference (DAC).

Sun, Z., Wu, W., and Li, H., 2013, "Cross-Layer Racetrack Memory Design For Ultra High Density And Low Power Consumption," 50th Annual Design Automation Conference (DAC).

Wang, J., Sun, Z., Li, H., and Wong, W.F., 2013, "Practical Low-Power Memristor-based Analog Neural Branch Predictor," International Symposium on Low Power Electronics and Design (ISLPED), pp. 175-180.

Zhang, Y., Bayram, I., Wang, Y., Li, H., and Chen, Y., 2013, "ADAMS: Asymmetric Differential STT-RAM Cell Structure For Reliable and High-performance Applications," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 9-16.

Zhang, Y., Bayram, I., Wang, Y., Li, H., and Chen, Y., 2013, "ADAMS: Asymmetric Differential STT-RAM Cell Structure for Reliable and High-performance Applications," International Workshop on Design Automation for Analog and Mixed-Signal Circuits in conjunction with IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., and Li, H., 2013, "Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices," ACM Transactions on Design Automation of Electronic Systems (TODAES), no.4, p. 57.

Li, H., 2012, "Memristor in Neuromorphic Computing," 25th IEEE International SoC Conference (SoCC 2012), p. 294.

Li, H., and Pino, R.E., 2012, "Statistical Memristor Model and Its Applications in Neuromorphic Computing. ISBN 978-94-007-4490-5," in Advances in Neuromorphic Memristor Science and Applications, R. Kozma, G. Pazienza, and R.E. Pino, eds., Springer.

Li, H., and Sun, Z., 2012, "Voltage Driven Non-destructive Self-reference Sensing for STT-RAM Yield Enhancement," Spin, no.3, p. 124008, DOI: 10.1142/S2010324712400085.

Li, H., Pino, R., Chen, Y., Hu, M., and Liu, B., 2012, "Statistical Memristor Modeling and Case Study in Neuromorphic Computing," Design Automation Conference (DAC), pp. 585-590.

Li, H., Sun, Z., Bi, X., Wong, W.F., Zhu, X., and Wu, W., 2012, "STT-RAM Cache Hierarchy Design and Exploration with Emerging Magnetic Devices," in Nonvolatile Memory Technologies, Y. Xie, ed., Springer.

Bi, X., Li, H., and Kim, J.J., 2012, "Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 374-379.

Bi, X., Li, H., and Wang, X., 2012, "STT-RAM Cell Design Considering CMOS and MTJ Temperature Dependence," IEEE Transactions on Magnetics (TMAG), no.11, pp. 3821-3824.

Bi, X., Sun, Z., Li, H., and Wu, W., 2012, "Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches," International Conference on Computer Aided Design (ICCAD), pp. 88-94.

Bi, X., Zhang, C., Li, H., Chen, Y., and Pino, R., 2012, "Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference," Design, Automation & Test in Europe (DATE), pp. 1301-1306, Dresden, Germany.

Chen, X., Zeng, J., Chen, Y., Li, H., Zhang, W., Liao, S.W., and Wang, J., 2012, "Fine-grained Dynamic Voltage Scaling on OLED Display," 17th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 807-812.

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., and Zhang, T., 2012, "A 130nm 1.2V/3.3V 16 Kb Spin-Transfer Torque Random Access Memory with Nondestructive Self-Reference Sensing Scheme," IEEE Journal of Solid-State Circuits (JSSC), no.2, pp. 560-573.

Chen, Y., Li, H., Xie, Y., and Niu, D., 2012, "Low Power Design of Emerging Memory Technologies. ISBN: 978-14-398-5040-4," in Handbook of Energy-Aware and Green Computing, I. Ahmad, and S. Ranka, eds., CRC Press.

Chen, Y., and Li, H., 2012, "The Optimization of STT-RAM Read/Write and Design Consideration with MTJ Temperature Dependence," in Spintronic module, X. Wang, ed., ELSEVIER.

Chen, Y.C., Li, H., and Zhang, W., 2012, "A Novel Peripheral Circuit for RRAM-based LUT," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1811-1814, Seoul, Korea.

Chen, Y.C., Zhang, W., and Li, H., 2012, "A Look Up Table Design with 3D Bipolar RRAMs," 17th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 73-78.

Chen, Y.C., Zhang, W., and Li, H., 2012, "Non-volatile 3D stacking RRAM-based FPGA," 22nd International Conference on Field Programmable Logic and Applications (FPL), pp. 367-372.

Chen, Y.C., Zhang, W., and Li, H., 2012, "Run-time Reconfigurable Architecture based on RRAM-based FPGA," International Conference on Field-Programmable Technology (FPT).

Hu, M., Li, H., Wu, Q., and Rose, G., 2012, "Hardware Realization of Neuromorphic BSB Model with Memristor Crossbar Network," Design Automation Conference (DAC), pp. 498-503.

Hu, M., Li, H., Wu, Q., Rose, G., and Chen, Y., 2012, "Memristor Crossbar Based Hardware Realization of BSB Recall Function," International Joint Conference on Neural Networks (IJCNN), pp. 1-7.

Sun, Z., Li, H., and Wu, W., 2012, "A Dual-mode Architecture for Fast-switching STT-RAM," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 45-50.

Sun, Z., Li, H., Chen, Y., and Wang, X., 2012, "Voltage Driven Non-Destructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory," IEEE Transactions on Very Large Scale Integration (TVLSI), no.11, pp. 2020-2030.

Sun, Z., Li, H., Wang, X., and Chen, Y., 2012, "MTJ Design Margin Exploration for Self-Reference Sensing," Journal of Applied Physics (JAP), 07C726.

Sun, Z., Bi, X., and Li, H., 2012, "Process Variation Aware Data Management for STT-RAM Cache Design," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 179-184.

Sun, Z., Chen, X., Zhang, Y., Li, H., and Chen, Y., 2012, "Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder," ACM Journal on Emerging Technologies in Computing Systems (JETC), no.2, article no.13.

Wang, H., Li, H., and Pino, R.E., 2012, "Memristor-based Synapse Design and Training Scheme for Neuromorphic Computing Architecture," International Joint Conference on Neural Networks (IJCNN), pp. 1-5.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., and Li, H., 2012, "Architecting a Common-source-line Array for Bipolar Nonvolatile Memory Devices," Design, Automation & Test in Europe (DATE), pp. 1451-1454, Dresden, Germany.

Li, H., and Chen, Y., 2011, "Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing. ISBN:978-14-398-0745-3," CRC Press.

Li, H., Wang, X., Ong, Z.L., Wong, W.F., Zhang, Y., Wang, P., and Chen, Y., 2011, "Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subjective to Architecture-level Requirement," IEEE Transactions on Magnetics (TMAG), no.10, pp. 2356-2359.

Chen, Y., and Li, H., 2011, "Emerging Sensing Techniques for Emerging Memories," "Emerging Sensing Techniques for Emerging Memories," pp. 204-210.

Chen, Y., and Li, H., 2011, "Emerging Sensing Techniques for Emerging Memories," 16th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 204-210.

Chen, Y., Wong, W.F., Li, H., and Koh, C.K., 2011, "Design of Processor Caches with Multi-Level Spin-Transfer Torque RAM Cells," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 73-78.

Chen, Y.C., Li, H., Chen, Y., and Pino, R., 2011, "3D-ICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory," Design, Automation & Test in Europe Conference and Exhibition (DATE), pp. 1-4.

Chen, Y.C., Li, H., Zhang, W., and Pino, R., 2011, "3D-HIM: A 3-Dimensional High-Density Interleaved Memory for Bipolar RRAM Design," IEEE/ACM International Symposium on Nanosclae Architectures (NANOARCH), pp. 59-64.

Dong, X., Wu, X., Xie, Y., Chen, Y., and Li, H., 2011, "Stacking MRAM atop Microprocessors: An Architecture-Level Evaluation," IET Computers & Digital Techniques (IET-CDT), no.3, pp. 213-220.

Hu, M., Li, H., and Pino, R.E., 2011, "Multi Retention Level STT-RAM Cache Designs," International Conference on Computer Aided Design (ICCAD), pp. 345-352.

Hu, M., Li, H., Chen, Y., and Wang, X., 2011, "Spintronic Memristor: Compact Model and Statistical Analysis," Journal of Low Power Electronics (JOLPE), pp. 234-244.

Hu, M., Li, H., Chen, Y., Wang, X., and Pino, R.E., 2011, "3D-ICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory," 16th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 25-30.

Joshi, R., Kanj, R., Wang, P., and Li, H., 2011, "Universal Statistical Cure For Predicting Memory Loss," International Conference on Computer Aided Design (ICCAD), pp. 236-239.

Sun, Z., Bi, X., Li, H., Wong, W.F., Ong, Z.L., Zhu, X., and Wu, W., 2011, "Multi Retention Level STT-RAM Cache Designs," IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 329-338.

Wang, P., Chen, X., Chen, Y., Li, H., Kang, S., Zhu, X., and Wu, W., 2011, "A 1.0 V 45nm Nonvolatile Magnetic Latch Design and Its Robustness Analysis," IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4.

Wang, P., Wang, X., Zhang, Y., Li, H., and Chen, Y., 2011, "Nonpersistent Errors Optimization in Spin-MOS Logic and Storage Circuitry," IEEE Transaction on Magnetics (TMAG), no.10, pp. 3860-3863.

Xue, J., Zhang, Y., Chen, Y., Sun, G., Yang, J.J., and Li, H., 2011, "Emerging Non-Volatile Memories: Opportunities and Challenges," ACM Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS'11), pp. 325-334.

Zhang, Y., Wang, X., Li, H., and Chen, Y., 2011, "STT-RAM Cell Optimization Considering Process Variations," IEEE Transaction on Magnetics (TMAG), no.10, pp. 2962-2965.

Zhu, W., Li, H., and Wang, X., 2011, "Current Switching in MgO-based Magnetic Tunneling Junctions," IEEE Transaction on Magnetics (TMAG), no.1, pp. 156-160.

Li, H., and Chen, Y., 2010, "Emerging Non-Volatile Memory Technologies - From Materials, to Device, Circuit, and Architecture," 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4.

Li, H., and Hu, M., 2010, "Compact Model of Memristors and Its Application in Computing Systems," Design, Automation & Test in Europe Conference and Exhibition (DATE), pp. 673-678.

Chen, Y., Li, H., and Wang, X., 2010, "Spintronic Devices: from Memory to Memristor," International Conference on Communications, Circuits and Systems (ICCCAS), pp. 961-963.

Chen, Y., Li, H., Chen, C.K., Roy, K., Li, J., and Sun, G., 2010, "Variable-Latency Adder (VL-Adder): New Arithmetic Circuit Design Practice for Low Power and NBTI Tolerance," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, no.11, pp. 1621-1624.

Chen, Y., Li, H., Sun, Z., Wang, X., Zhu, W., Sun, G., and Xie, Y., 2010, "Access Scheme of Multi-Level Cell Spin-Transfer Torque Random Access Memory and Its Optimization," 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1109-1112.

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., and Zhang, T., 2010, "A Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM)," Design, Automation & Test in Europe (DATE), pp. 148-153, Dresden, Germany.

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., and Zhang, T., 2010, "Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 1-6.

Chen, Y., and Li, H., 2010, "Patents Relevant to Cross-point Memory Array."

Chen, Y., Tian, W., Li, H., Wang, X., and Zhu, W., 2010, "PCMO Device with High Switching Stability," IEEE ELectron Device Letters (EDL), no.8, pp. 866-868.

Chen, Y., Tian, W., Li, H., Wang, X., and Zhu, W., 2010, "Scalability of PCMO-based Resistive Switch Device in DSM Technologies," International Symposium on Quality Electronic Design (ISQED), pp. 327-332.

Chen, Y., Wang, X., Li, H., and Park, J., 2010, "Applications of TMR Devices in Solid State Circuits and Systems," International SoC Design Conference (ISOCC).

Chen, Y., Wang, X., Sun, Z., and Li, H., 2010, "The Application of Spintronic Devices in Magnetic Bio-sensing," Asia Symposium on Quality Electronic Design (ASQED), pp. 230-234.

Chen, Y., Wang, Y., Li, H., Xi, H., Zhu, W., and Yan, Y., 2010, "Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, no.12, pp. 1724-1734.

Sun, G., Joo, Y., Chen, Y., Xie, Y., Chen, Y., and Li, H., 2010, "A Hybrid Solid-State Storage Architecture for the Performance, Energy Consumption, and Lifetime Improvement," International Symposium on High-Performance Computer Architecture (HPCA), pp. 141-152.

Sun, Z., Li, H., Chen, Y., and Wang, X., 2010, "Variation Tolerant Sensing Scheme of Spin-Transfer Torque Memory for Yield Improvement," International Conference on Computer Aided Design (ICCAD), pp. 432-437.

Wang, X., Chen, Y., Gu, Y., and Li, H., 2010, "Spintronic Memristor Temperature Sensor," IEEE Electron Device Letters (EDL), no.1, pp. 20-22.

Xi, H., Stricklin, J., Li, H., Chen, Y., Wang, X., Zheng, Y., Gao, Z., and Tang, M.X., 2010, "Spin Transfer Torque Memory with Thermal Assist Mechanism: A Case Study," IEEE Transactions on Magnetics (TMAG), no.3, pp. 860-865.

Li, H., and Chen, Y., 2009, "An Overview of Non-Volatile Memory Technology and the Implication for Tools and Architectures," Design, Automation & Test in Europe (DATE) 2009, pp. 731-736.

Li, H., Xi, H., Chen, Y., Wang, X., and Zhang, T., 2009, "Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 217-222.

Chen, Y., Li, H., Chen, C.K., and Roy, K., 2009, "Gated Decap: Gate Leakage Control of On-chip Decoupling Capacitors in Scaled Technologies," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, no.12, pp. 1749-1752.

Koh, C.K., Wong, W.F., Chen, Y., and Li, H., 2009, "A Hybrid Solid-State Storage Architecture for the Performance, Energy Consumption, and Lifetime Improvement," International Conference on Computer Design (ICCD), pp. 268-274.

Koh, C.K., Wong, W.F., Chen, Y., and Li, H., 2009, "Tolerating process variations in large, set associative caches: The buddy cache," ACM Transactions on Architecture and Code Optimization (TACO), no.8, 34 pages.

Wang, X., Xi, H., Chen, Y., Li, H., and Dimitrov, D.V., 2009, "Spintronic Memristor through Spin Torque Induced Magnetization Motion," IEEE ELectron Device Letters (EDL), no.3, pp. 294-297.

Li, H., Patel, R., Sit, K., Tang, Z., and Jamshidi, S., 2008, "Design for Low Power. ISBN 978-08-493-0885-7," in The Computer Engineering Handbook, 2nd edition, V. Oklobdzija, ed., CRC Press.

Chen, Y., Wang, X., Li, H., Liu, H., and Dimitrov, D., 2008, "Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)," International Symposium on Quality Electronic Design (ISQED), pp. 684-690.

Dong, X., Wu, X., Sun, G., Chen, Y., Li, H., and Xie, Y., 2008, "Circuit and Microarchitecture Evaluation of Magnetic RAM (MRAM) as a Universal Memory Replacement," IEEE Design Automation Conference (DAC), pp. 554-559.

Wang, X., Chen, Y., Li, H., Liu, H., and Dimitrov, D., 2008, "Spin Torque Random Access Memory down to 22nm Technology," IEEE Transaction on Magnetics (TMAG), no.11, pp. 2479-2482.

Chen, Y., Li, H., Li, J., and Koh, C.K., 2007, "Variable-latency Adder (VL-Adder): New Arithmetic Circuit Design Practice to Overcome NBTI," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 195-200.

Koh, C.K., Wong, W.F., Chen, Y., and Li, H., 2007, "VOSCH: Voltage Scaled Cache Hierarchies," International Conference on Computer Design (ICCD), pp. 496-503.

Li, H., Chen, Y., Roy, K., and Koh, C.K., 2006, "SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design," Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 158-163.

Li, H., Cher, C.Y., Vijaykumar, T.N., and Roy, K., 2005, "Combined Circuit and Architectural Level Variable Supply-Voltage Scaling for Low Power," IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, no.5, pp. 564-576.

Chen, Y., Li, H., Roy, K., and Koh, C.K., 2005, "Cascaded Carry-Select Adder (C2SA): A New Structure for Low-Power CSA Design," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 115-118.

Chen, Y., Li, H., Roy, K., and Koh, C.K., 2005, "Gated Decap: A Technique to Reduce Gate Leakage in Decoupling Capacitors in Scaled Technologies," IEEE Custon Integrated Circuits Conference (CCC), pp. 775-778.

Li, H., Bhunia, S., Chen, Y., Vijaykumar, T.N., and Roy, K., 2004, "DCG: Deterministic Clock Gating For Low-Power Microprocessor Design," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, no.3, pp. 245-254.

Li, H., Bhunia, S., Chen, Y., Vijaykumar, T.N., and Roy, K., 2003, "Deterministic Clock Gating for Microprocessor Power Reduction," 9th International Symposium on High-Performance Computer Architecture (HPCA), pp. 113-122.

Li, H., Cher, C.Y., Vijaykumar, T.N., and Roy, K., 2003, "VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power," 36th IEEE/ACM International Symp. on Microarchitecture (MICRO), pp. 19-28.

Agarwal, H., Li, H., and Roy, K., 2003, "A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron," IEEE Journal of Solid-State Circuits (JSSC), no.2, pp. 319-328.

Agrawal, A., Li, H., and Roy, K., 2002, "DRG-Cache: A Data Retention Gated-Ground Cache for Low Power," 39th Design Automation Conference (DAC), pp. 473-478.

Bhunia, S., Li, H., and Roy, K., 2002, "A High Performance IDDQ Testable Cache for Scaled CMOS Technologies," IEEE 11th Asian Test Symposium (ATS), pp. 157-162.

Li, H., Agrawal, A., Chen, Y., and Roy, K., 2001, "DRG-Cache: A Single Vt Low Leakage Cache for Deep Sub-micron."

Li, H., Wang, J., and Liu, Z., 2000, "An Optimal Strategy for Parameter Extraction of BSIM3V3 Model," Microelectronics (in Chinese), no.6, pp. 387-390.

"A Magnetic Moment: Prospects for MRAM Technology, Markets and Applications."

Li, H., 2014, "Design Challenges in MLC STT-RAM Caches," Institute of Computing Technology, Chinese Academy of Sciences.

Li, H., 2014, "Emerging Memristor Technology Enabled Next Generation Cortical Processor," IEEE International System-on-Chip Conference (SOCC), Las Vegas, Nevada.

Li, H., 2014, "Emerging Technology Enabled Next Generation Cortical Processor," Machine Intelligence from Cortical Networks (MICrONS) workshop, Arlington, Virginia.

Li, H., 2014, "Memristor Modeling -- Static, Statistical, and Stochastic Methodologies," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, Florida, USA.

Li, H., 2014, "Neuromorphic Hardware Acceleration Enabled by Emerging Technologies," International Symposium on Integrated Circuits (ISIC), Singapore.

Li, H., 2014, "Phase Change Memory, Resistive Memory, and Memristor," School of Information Science and Technology, University of Chinese Academy of Sciences, Beijing, China.

Li, H., 2014, "Unleashing the Potential of Multi-level Cells in STT-RAM Caches," CRAW/CDC Discipline Specific Workshop on Diversity in Design Automation Conference (DAC), San Francisco, CA.

Li, H., 2014, "Von Neumann & Neuromorphic Systems atop Spintronic and Resistive Devices," Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA.

Li, H., 2014, "Von Neumann and Neuromorphic Systems Leveraging the Emerging Nonvolatile Devices," Tsinghua University.

Li, H., 2013, "An Adaptive Information Processing System Resilient to Device Variations and Noises," DARPA, Arlington, VA.

Li, H., 2013, "Design Space Exploration and Applications of STT-RAM in Modern Computing Systems," Cisco Inc..

Li, H., 2013, "Emerging Memristor Technology and Its Usage in Neuromorphic Systems," School of Electronic Science and Engineering, Nanjing University.

Li, H., 2013, "General Realization of Neuromorphic Computing Systems Based on Stochastic Characteristics of Memristive Switches," Air Force Research Lab (AFRL), Rome.

Li, H., 2013, "Neuromorphic Systems atop Emerging Devices," National Cheng Kung University.

Li, H., 2013, "Next-generation Array & Tape Organizations for Revolutionary Spintronic," Department of Computer Science, School of Computing, NAtional University of Singapore.

Li, H., 2013, "Stay Spinning, Stay Cool!," Department of Computer Science, City University of Hong Kong, Hong Kong.

Li, H., 2013, "Terminator: Next-generation Array and Tape Organizations for Revolutionary Spintronic," Cloud, Storage, Big Data Summit jointly held with the 2nd Asian Nonvolatile Memory Workshop (ANVMW), Shanghai, China.

Li, H., 2013, "Terminator: Next-generation Array and Tape Organizations for Revolutionary Spintronic," EDA Workshop 2013, Kyoto Research Park, Kyoto, Japan.

Li, H., 2013, "Terminator: Next-generation Array and Tape Organizations for Revolutionary Spintronic," The 5th International Workshop on Emerging Circuits and Systems (IWECS), Chengdu, China.

Li, H., 2013, "Terminator: Next-generation Array and Tape Organizations for Revolutionary Spintronic," Tutorial, Qualcomm Inc., San Diego, CA.

Li, H., 2013, "The Stochastic Characteristics of Memristor Devices and Case Studies in Neuromorphic Hardware De-sign," International Semiconductor Device Research Symposium (ISDRS), Maryland.

Hu, M., Li, H., Chen, Y., Rose, G., and Wu, Q., 2013, "BSB Training Scheme Implementation on Memristor-Based Circuit," 2013 Sympsoium Series on Computational Intelligence.

Li, H., 2012, "Emerging Memory Design and Applications," Tsinghua University.

Li, H., 2012, "Evolution or Revolution: NVM-enabled Transition from von Neumann Architecture to Neuromorphic Hardware," Department of Computer Science, School of Computing, National University of Singapore.

Li, H., 2012, "Memristor in Neuromorphic Computing," 25th IEEE International SoC Conference (SoCC), Niagara Fall, NY.

Li, H., 2012, "Pipelined Memory Access Method and Architecture Therefore," IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Xi'an, China.

Li, H., 2012, "Probabilistic Design to Improve Runtime Stability and Performance of STT-RAM," IBM T. J. Watson, New York.

Li, H., 2012, "Runtime Programmable FPGA Architecture based on Nanoscale RRAM," Network Science and Reconfigurable Systems for Cyber Security (NSRSC) Conference, Washington DC.

Li, H., 2012, "Stay Spinning, Stay Cool!," A*STAR Data Storage Institute (DSI), Singapore.

Li, H., 2012, "STT-RAM Research of Pitts and NYU-Poly Team," the Samsung Memory Division, Dongtan, Korea.

Bi, X., Li, H., and Wang, X., 2012, "STT-RAM Design Considering Temperature Impact," IEEE International Magnetics Conference (InterMag).

Chen, Y.C., Li, H., and Zhang, W., 2012, "A RRAM-based Memory System and Applications," The Non-Volatile Memories Workshop (NVMW).

Hu, M., and Li, H., 2012, "Low Power Neuromorphic Circuit Using Memristor Crossbar Array," ACM Student Research Competition at DAC 2012.

Sun, Z., Bi, X., Li, H., Wong, W.F., Zhu, X., and Wu, W., 2012, "Multi Nonvolatility Level STTRAM Cache Hierarchy," The Non-Volatile Memories Workshop (NVMW).

Li, H., 2011, "An Overview of STT-RAM Technology - from Device Modeling to Applications," Princeton/Central New Jersey Chapter of the IEEE SSCS Chapter (Solid-State Circuits Society), Rutgers University, Piscataway, NJ.

Li, H., 2011, "Application of Spintronic for MRAM and Memristor-based Computing," International Symposium on Quality Electronic Design (ISQED), San Jose, CA.

Li, H., 2011, "Emerging Sensing Techniques for Emerging Memories," the 16th Asia and South Pacific Design Automation Conference (ASP-DAC).

Li, H., 2011, "Integrating Emerging Memory on Top of CMP: Opportunities and Challenge," D43D: 4th Design for 3D Silicon Integration Workshop, MINATEC, Grenoble, France.

Li, H., 2011, "Memristor and Its Applications in Neuromorphic and Reconfigurable Computing Platform," Air Force Research Lab (AFRL), Dayton, OH.

Li, H., 2011, "Memristor-Based 3D Neuromorphic Computing Architectures," Workshop on Future Perspectives of Neuromorphic Memristor Science & Technology, collated with International Joint Conference on Neural Networks (IJCNN), San Jose, CA.

Li, H., 2011, "Memristor-Based Computing Architecture: Design Methodology & Circuit Techniques," Boise State University.

Li, H., 2011, "Memristor-Based Reconfigurable Design for Neuromorphic Computing Architecture," Air Force Research Lab (AFRL), Rome, NY.

Li, H., 2011, "Spintronic Devices - the Future Storage and Computing Elements in Computing Systems," International ASIC Conference (ASICON).

Li, H., 2011, "STT-RAM Technology: Device, Circuit, and System Applications," Qualcomm Inc., San Diego, CA.

Li, H., 2011, "STT-RAM Technology: Device, Circuit, Architecture and Applications," Avalanche Inc., Fremont, CA.

Li, H., Wang, X., Ong, Z.L., Wong, W.F., Zhang, Y., Wang, P., and Chen, Y., 2011, "Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subjective to Architecture-level Requirement," IEEE International Magnetics Conference (InterMag).

Bi, X., Li, H., and Wang, X., 2011, "Design Considerations for Thermal-assistant STT-RAM through Joule Heating," the 56th Magnetism Materials Conference (MMM).

Chen, Y., Wang, X., Wong, W.F., and Li, H., 2011, "Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subjective to Architecture-level Requirement," The Non-Volatile Memories Workshop (NVMW).

Hu, M., Li, H., Chen, Y., and Pino, R.E., 2011, "Statistical Model of TiO2 Memristor," the 48th Design Automation Conference (DAC), in WIP track.

Sun, Z., Li, H., and Wang, X., 2011, "MTJ Design Margin Exploration for Self-Reference Sensing," the 56th Magnetism Materials Conference (MMM).

Wang, P., Wang, X., Zhang, Y., Li, H., and Chen, Y., 2011, "Spin-MOS Logic and Storage Circuitry Optimization for Non-persistent Error Rate Reduction," IEEE International Magnetics Conference (InterMag).

Zhang, Y., Chen, Y., Wang, X., and Li, H., 2011, "STT-RAM Cell Optimization Considering Process Variations," The Non-Volatile Memories Workshop (NVMW).

Zhang, Y., Wang, X., Li, H., and Chen, Y., 2011, "STT-RAM Cell Optimization Considering Process Variations," IEEE International Magnetics Conference (InterMag).

Li, H., 2010, "Compact Model of Memristors and Its Application in Computing Systems," Design, Automation & Test in Europe Conference and Exhibition (DATE).

Li, H., 2010, "Emerging Non-Volatile Memory Technologies - From Materials, to Device, Circuit, and Architecture," the 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).

Li, H., 2010, "Memristor-Based Computing Architecture: Design Methodology & Circuit Techniques," Air Force Research Lab (AFRL), Rome.

Sun, Z., Li, H., and Wang, X., 2010, "Magnetic Bio-sensing based on Spintronic Memristor," International Workshop on Biomedical System Design.

Li, H., 2009, "An Overview of Non-Volatile Memory Technology and the Implication for Tools and Architectures," Design, Automation & Test in Europe (DATE).

Li, H., 2009, "Spin-Transfer Torque Random Access Memory - Device, Circuit and Architecture," Department of Electrical and Computer Engineering, Princeton University.

Li, H., 2009, "Spin-Transfer Torque Random Access Memory - Next Breakthrough in Embedded System," Department of Electrical and Computer Engineering, University of California, Sant Barbara.

Li, H., 2008, "Emerging Non-volatile Memory: Spin-Transfer Torque Memory and Resistive Memory," Department of Electronic Engineering, Tsinghua University.

Wang, X., Chen, Y., Li, H., Liu, H., and Dimitrov, D., 2008, "Spin Torque Random Access Memory down to 22nm Technology," IEEE International Magnetics Conference (InterMag).

Li, H., 2004, "Low-Power Design Technique at Circuit and Microarchitectural Boundary," the 7th SIGDA Ph.D. Forum at Design Automation Conference (DAC).

Li, H., Chen, Y., Liu, H., Kim, K.Y., Dimitrov, D., and Huang, H., 2014, "Spin-transfer Torque Memory Self-reference Read Method," US Patent 8,675,401.

Li, H., Chen, Y., Liu, H., and Huang, H., 2014, "Non-volatile Resistive Sense Memory On-Chip Cache," US Patent 8,650,355.

Li, H., Chen, Y., Yan, Y., Lee, B., and Wang, R., 2013, "Dual Stage Sensing for Non-volatile Memory," US Patent 8,537,587.

Chen, Y., Li, H., Liu, H., Dimitrov, D., Wang, X., Wang, X., 2013, "Predictive Thermal Preconditioning and Timing Control for Non-volatile memory Cells," US Patent 8,553,454.

Li, H., Chen, Y., Wang, A., Xi, H., Zhu, W., and Roelogs, A., 2013, "Quiescent Testing of Non-volatile Memory Array," US Patent 8,526,252.

Chen, Y., Li, H., Zhu, W., Wang, X., Wang, H., and Liu, H., 2013, "Spatial Correlation of Reference Cells in Resistive Memory Array," US Patent 8,526,215.

Li, H., 2013, "Transmission Gate-Based Spin-Transfer Torque Memory Unit," US Patent 8,416,615.

Chen, Y., Li, H., Liu, H., Wang, R., and Dimitrov, D., 2013, "Spin-transfer Torque Memory Non-destructive Self-reference Read Method," US Patent 8,416,614.

Wang, X., Chen, Y.Wang, X., Xi, H., Zhong, W., Li, H., and Liu, H., 2013, "Magnetic Tunnel Junction and Memristor Apparatus," US Patent 8,391,055.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., 2012, "Computer Memory Device with Multiple Interfaces," 8,194,914.

Li, H., Chen, Y., Liu, H., Kim, K.Y., DImitrov, D., and Huang, H., 2012, "Spin-transfer Torque Memory Self-reference Read Method," 8,116,122.

Li, H., Chen, Y., Yan, Y., Lee, B., and Wang, R., 2011, "Dual Stage Sensing for Non-volatile Memory," 8,050,072.

Chen, Y., Li, H., Liu, H., Lu, Y., and Li, Y., 2011, "Transmission Gate-Based Spin-Transfer Torque Memory Unit," 7,974,119.

Chen, Y., Li, H., Zhong, W., WAng, X., and Wang, R., 2011, "Write Method with Voltage Line Tuning," 7,944,730.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., 2011, "Simultaneously Writing Multiple Addressable Blocks of User Data to a Resistive Sense Memory Cell Array," 7,944,729.

Wang, X., Chen, Y.Wang, X., Xi, H., Zhong, W., Li, H., and Liu, H., 2011, "Magnetic Tunnel Junction and Memristor Apparatus," 7,898,844.

Reed, D., Lu, Y., Carter, A., and Li, H., 2011, "Non-Volatile Memory Array with Resistive Sense Element Block Erase and Uni-Directional Write," 7,885,097.

Li, H., Chen, Y., Liu, H., and WAng, X., 2010, "Static Source Plane in ST-RAM," 7,859,891.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., 2010, "Resistive Sense Memory Array with Partial Block Update Capability," 7,830,700.

Xi, H., Liu, H., Wang, X., Lu, Y., Chen, Y., Zheng, Y., Dimitrov, D.V., Wang, D., and Li, H., 2010, "Variable Write and Read Methods for Resistive Random Access Memory," 7,826,255.

Liu, H., Lu, Y., Carter, A., Chen, Y., Li, H., and Xi, H., 2010, "Memory Array with Read Reference Voltage Cells," 7,755,923.

Sun, M., Jin, I., Vaithyanathan, V., Jung, C., Kim, Y.P., Amin, N., Tian, W., and Li, H., "Magic PMC Switch Fabrication Method and its Application as Selective Element for High Density Cross bar Memory Arrays," US Patent Pending 12/496,767.

Jiao, D., Li, H., Wang, R., Huang, H., and Chen, Y., "Integrated Circuit Active Power Supply Regulation," US Patent Pending, 12/501,375.

Chen, Y., Li, H., Zhu, W., WAng, X., Yan, Y., and Liu, H., "XRAM-Based Log Page for Flash Memory," US Patent Pending, 12/482,693.

Chen, Y., Li, H., Liu, H., and Wang, X., "Memory Hierarchy with Non-volatile Filter and Victim Caches," US Patent Pending, 12/269,535.

Li, H., Chen, Y., Wang, X., and Yan, Y., "Non-volatile Memory Having Increased Sensing Margin," US Patent Pending, 12/500,172.

Li, H., Chen, Y., Liu, H., Setiadi, D., and Lee, B., "Pipelined Memory Access Method and Architecture Therefore," US Patent Pending, 12/200,118.

Zhu, W., Li, H., Chen, Y., Wang, X., Huang, H., and Xi, H., 2012, "Memory Cell with Enhanced Read and Write Sense Margins," 8,199,562.

Chen, Y., Li, H., Liu, H., Wang, R., and Dimitrov, D., 2012, "Spin-transfer Torque Memory Non-destructive Self-reference Read Method," 8,116,123.

Wang, X., Chen, Y.Wang, X., Xi, H., Zhong, W., Li, H., and Liu, H., 2011, "Magnetic Tunnel Junction and Memristor Apparatus," 8,059,453.

Lu, Y., Liu, H., Li, H., Carter, A.J., Reed, D., and Xi, H., 2011, "Multi-Stage Parallel Data Transfer," 8,045,412.

Li, H., Chen, Y., Liu, H., Huang, H., and Wang, R., 2011, "Write Current Compensation Using Word Line Boosting Circuitry," 8,009,457.

Xi, H., Liu, H., Wang, X., Lu, Y., Chen, Y., Zheng, Y., Dimitrov, D.V., Wang, D., and Li, H., 2011, "Variable Write and Read Methods for Resistive Random Access Memory," 7,952,917.

Chen, Y., Li, H., Liu, H., Lu, Y., and Xue, S., 2011, "MRAM Diode Array and Access Method," 7,936,580.

Chen, Y., Li, H., Liu, H., DImitrov, D., and Wang, X., 2011, "Predictive Thermal Pre-Conditioning and Timing Control for Non-volatile Memory Cells," 7,916,528.

Chen, Y., Li, H., Zhu, W., Wang, X., Wang, R., and Liu, H., 2010, "Memory Cell with Proportional Current Self-Reference Sensing," 7,852,665.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., "Bit Set Modes for a Resistive Sense Memory Cell Array," US Patent Pending, 12/352,693.

Chen, Y., Li, H., Liu, H., and Wang, X., "Memory Hierarchy with Non-volatile Filter and Victim Caches," US Patent Pending, 12/332,669.

Chen, Y., Li, H., Zhu, W., Wang, X., Wang, H., and Liu, H., 2011, "Spatial Correlation Aware Reference Level Generation," 7,876,599.

Li, H., Chen, Y., Liu, H., Huang, H., and Wang, R., 2010, "Write Current Compensation Using Word Line Boosting Circuitry," 7,855,923.

Zhu, W., Li, H., Chen, Y., Wang, X., Huang, H., and Xi, H., 2010, "Enhancing Read and Write Sense Margins in a Resistive Sense Element," 7,852,660.

Huang, H., Li, H., and Lu, Y., 2010, "Data Storage Using Read-Mask-Write Operation," 7,830,726.

Chen, Y., Li, H., Liu, H., Huang, H., and Lu, Y., 2010, "Temperature Dependent Method of Reading STT-RAM," 7,755,965.

Chen, Y., Jin, I., Li, H., Wang, X., Dimitrov, D., and Wang, D., "Programmable Power Source Using Array of Resistive Sensing Memory Cells," US Patent Pending, 12/396,126.

Chen, Y., Li, H., Zhu, W., Wang, X., Yan, Y., and Liu, H., "Data Updating in Non-volatile Memory," US Patent Pending, 12/482,693.

Chen, Y., Li, H., Liu, H., Xi, H., and Xue, S., "Memory Hierarchy Containing Only Non-volatile Cache," US Patent Pending, 12/198,513.

Chen, Y., Li, H., Liu, H., Lu, Y., and Xue, S., 2012, "Data Devices Including Multiple Error Correction Codes and Methods of Utilizing," 8,296,620.

Chen, Y., Li, H., Liu, H., Lu, Y., and Xue, S., 2012, "MRAM Diode Array and Access Method," 8,289,746.

Reed, D., Lu, Y., Carter, A., and Li, H., 2012, "Non-Volatile Memory Array with Resistive Sense Element Block Erase and Uni-Directional Write," 8,213,259.

Wang, X., Li, H., and Liu, H., 2012, "Non-Volatile Memory Array with Resistive Sense Element Block Erase and Uni-Directional Write," 8,213,216.

Chen, Y., Li, H., Zhu, W., Wang, X., Wang, H., and Liu, H., 2012, "Spatial Correlation of Reference Cells in Resistive Memory Array," 8,139,397.

Li, H., Chen, Y., Liu, H., and Wang, X., 2012, "Static Source Plane in STRAM," 8,098,516.

Liu, H., Lu, Y., Carter, A., Chen, Y., Li, H., and Xi, H., 2012, "Memory Array with Read Reference Voltage Cells," 8,098,513.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., 2011, "Computer Memory Device with Status Register," 8,081,504.

Wang, A., Wang, X., Dimitrov, D., Li, H., Xi, H., and Liu, H., 2011, "Stuck-at Defect Condition Repair for A Non-volatile Memory Cell," 8,054,678.

Xi, H., Liu, H., Wang, X., Lu, Y., Chen, Y., Zheng, Y., Dimitrov, D.V., Wang, D., and Li, H., 2011, "Variable Write and Read Methods for Resistive Random Access Memory," 8,054,675.

Wang, X., Lu, Y., Li, H., and Liu, H., 2011, "Three Dimensionally stacked non volatile memory unit," 8,054,673.

Chen, Y., Li, H., Liu, H., Kim, K., and Huang, H., 2011, "Pipeline Sensing Using Voltage Storage Elements to Read Non-volatile Memory Cells," 7,936,625.

Li, H., Chen, Y., Liu, H., and Wang, X., 2011, "Non-volatile Memory Read/Write Verify," 7,898,844.

Huang, H., Li, H., and Lu, Y., 2011, "Data Storage Using Read-Mask-Write Operation," 8,289,786.

Chen, Y., Li, H., Zhu, W., Wang, X., Huang, H., and Liu, H., 2012, "Resistive Sense Memory Calibration for Self-Reference Read Method," 8,213,215.

Chen, Y., Li, H., Zhu, W., Wang, X., Wang, R., and Liu, H., 2012, "Memory Cell with Proportional Current Self-Reference Sensing," 8,203,899.

Li, H., Chen, Y., Liu, H., Huang, H., and Wang, R., 2012, "Write Current Compensation Using Word Line Boosting Circuitry," 8,203,893.

Chen, Y., Li, H., Zhu, W., Wang, X., Yan, Y., and Liu, H., 2012, "Voltage Reference Generation with Selectable Dummy Regions," 8,203,862.

Chen, Y., Li, H., Liu, H., Lu, Y., and Li, Y., 2012, "Transmission Gate-Based Spin-Transfer Torque Memory Unit," 8,199,563.

Chen, Y., Li, H., Liu, H., Dimitrov, D., Wang, X., Wang, X., 2012, "Predictive Thermal Preconditioning and Timing Control for Non-volatile memory Cells," 8,154,914.

Li, H., Chen, Y., Liu, H., and WAng, X., 2011, "Static Source Plane in ST-RAM," 8,068,359.

Huang, H., Li, H., and Lu, Y., 2011, "Data Storage Using Read-Mask-Write Operation," 8,040,743.

Li, H., Chen, Y., Liu, H., Huang, H., and Wang, R., 2011, "Write Current Compensation Using Word Line Boosting Circuitry," 7,974,121.

Chen, Y., Setiadi, D., Li, H., Xi, H., and Liu, H., 2011, "Generic Non-volatile Service Layer," 7,966,581.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., 2011, "Resistive Sense Memory Array with Partial Block Update Capability," 7,944,731.

Wang, X., Li, H., and Liu, H., 2011, "Shared Bit Line and Source Line Resistive Sense Memory Structure," 7,940,548.

Li, H., Chen, Y., Setiadi, D., Liu, H., and Lee, B., 2011, "Defective Bit Scheme for Multi-Layer Integrated Memory Device,," 7,936,622.

Liu, H., Lu, Y., Carter, A., Chen, Y., Li, H., and Xi, H., 2011, "Memory Array with Read Reference Voltage Cells," 7,936,588.

Chen, Y., Li, H., Zhu, W., Wang, X., Huang, H., and Liu, H., 2011, "Resistive Sense Memory Calibration for Self-Reference Read Method," 7,898,838.

Wang, A., Wang, X., Dimitrov, D., Li, H., Xi, H., and Liu, H., 2011, "Stuck-at Defect Condition Repair for A Non-volatile Memory Cell," 7,894,250.

Chen, Y., Li, H., Liu, H., Kim, K., and Huang, H., 2011, "Voltage Reference Generation for Resistive Sense Memory Cells," 7,881,094.

Chen, Y., Li, H., Liu, H., WAng, R., and Dimitrov, D., "Spin-Transfer Torque Memory Non-Destructive Self-Reference Read Method," International Patent Pending, PCT/US09/38935.

Wang, X., Lu, Y., Li, H., and Liu, H., 2013, "Three Dimensionally Stacked Non-volatile Memory Unit," US Patent 8,482,957.

Sun, M., Amin, N., Jin, I., Kim, Y.P., Jung, C., Vaithyanathan, V., Tian, W., and Li, H., 2013, "Programmable metallization cell switch and memory units containing the same," US Patent 8,446, 752.

Li, H., Chen, Y., Liu, H., Kim, K.Y., Dimitrov, D., and Huang, H., 2013, "Spin-transfer Torque Memory Self-reference Read Method," US Patent 8,411,495.